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Semiconductor device, reset control system and memory reset method

A technology of reset control and memory, applied in static memory, memory system, read-only memory, etc., can solve the problems of electronic equipment failure, bad flash ROM, etc., and achieve the effect of preventing the continuous state that cannot be reset

Inactive Publication Date: 2006-04-26
FUJITSU LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this way, the flash ROM that has been reset during erasing is over-erased and cannot be rewritten, and the electronic device is equipped with a defective flash ROM, which causes failure of the electronic device.

Method used

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  • Semiconductor device, reset control system and memory reset method
  • Semiconductor device, reset control system and memory reset method
  • Semiconductor device, reset control system and memory reset method

Examples

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Embodiment Construction

[0035] [The first embodiment of the present invention]

[0036] Figure 6 The first embodiment of the present invention is shown.

[0037] The semiconductor device 6 in the first embodiment of the present invention is configured not to supply a reset signal to the flash ROM 14 while the flash ROM 14 is being erased.

[0038] The semiconductor device 6 is composed of an external reset terminal 7, a reset input control circuit 8, a command control circuit 10, a timer 11, a CPU 12, a flash I / F 13 (interface), and a flash ROM 14.

[0039] The reset input control circuit 8 receives a reset signal from the outside through the external reset terminal 7 , and supplies the external reset signal RSTEX to the clock circuit 9 .

[0040] The clock circuit 9 synchronizes the external reset signal RSTEX from the reset input control circuit 8 with the clock signal, and supplies internal circuits including the flash ROM 14 as an internal reset signal RSTIX.

[0041]Flash I / F 13 is arranged ...

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Abstract

A semiconductor device having a nonvolatile memory comprises a reset input control circuit that does not supply any reset signal to the nonvolatile memory while a BUSY / READY signal from the nonvolatile memory is active even if a reset signal is supplied from outside. Since the nonvolatile memory is not reset while the nonvolatile memory is doing an erase processing because of the provision of the reset input control circuit, overerase of the nonvolatile memory can be prevented.

Description

technical field [0001] The present invention relates to a semiconductor device mounted with an electrically erasable and writable nonvolatile memory. Background technique [0002] Non-volatile memory is different from semiconductor memory that requires power support such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory: Static Random Access Memory), and it will not change even if the power is turned off. Eliminate data storage. In recent years, nonvolatile memories, especially flash ROMs (FlashROM, ROM: Read Only Memory) have been widely used in mobile phones, HDDs, and the like due to their characteristics, and their applications are expanding. [0003] The gate of the memory cell of the nonvolatile memory adopts a double-layer structure of a control gate and a floating gate. Data is written by injecting electrons into the floating gate, and data is erased by taking electrons out of the floating gate. Specifically, charge extraction for erasin...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/16G06F12/00G11C16/02G11C16/20G11C16/34
CPCG11C16/20G11C16/3468G11C16/3477
Inventor 松浦修
Owner FUJITSU LTD
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