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Testing ram address decoder for resistive open defects

An address and electronic circuit technology, used in the field of testing integrated circuits such as semiconductor memory address decoders or random logic circuits, which can solve problems such as user return and reliability issues

Inactive Publication Date: 2006-06-21
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0016] These types of defects lead to significant user return and reliability issues

Method used

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  • Testing ram address decoder for resistive open defects
  • Testing ram address decoder for resistive open defects
  • Testing ram address decoder for resistive open defects

Examples

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Embodiment Construction

[0051] See Figure 3 of the accompanying drawings, which shows a typical address decoder with NMOS and CMOS logic implementations. The NMOS gate uses a depletion mode NMOS load transistor and a switching enhancement mode transistor. In contrast, fully static CMOS logic gates are constructed from an equal number of enhancement-mode PMOS and NMOS transistors.

[0052] The address decoder selects a word line according to an input address. This requires that the logic gate output in the address decoder is only valid for the unique input address and invalid for the rest of the addresses. For example, for the NAND gates in Figure 3, the output is active (logic 0) only when all gate inputs are high, and inactive (logic 1) the rest of the time.

[0053] In NMOS technology, a depletion-mode load transistor pulls the output up to an inactive state when the input cannot activate the gate. An open defect in the switch transistor of an NMOS logic gate keeps the gate inactive when it shou...

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PUM

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Abstract

For example, a hard open defect between the logic gates of the address decoder and the voltage source causes logical and sequential delays in operation, rendering the memory conditionally inoperable. The present invention provides a method and apparatus for testing integrated circuits for these types of defects in which two cells in logically adjacent rows or columns are written with complementary logical data. If the read operation shows that the data in the two cells is the same, it indicates the presence and location of a hard open defect. The read and write operations each occur as a result of a clock pulse, and the method includes the step of setting the clock period such that, in the case of said first cell indicating a slow-down action, after the logic state of said first cell has fallen to before its minimum value, will cause a read cycle to be performed; and / or set the width of the clock pulse such that in the case of the first cell indicating a slow-rising action, the logic state of the first cell has risen to its maximum value, will cause the read loop to execute.

Description

technical field [0001] The present invention relates to a method and apparatus for testing integrated circuits such as semiconductor memory address decoders or random logic circuits, and more particularly to a method and apparatus for testing such circuits in the presence of open circuit defects. Background technique [0002] The systematic and automated testing of electronic circuits and especially integrated circuits is becoming increasingly important. Each generation of circuits tends to include higher component densities and increased amounts of system functionality. Individual circuits have become so complex that process defects cannot be detected and located except through exhaustive and expensive testing. It is clearly not desirable for consumers to accept circuit products whose hidden defects are only exposed during operational use, thereby appearing, for example, as life support systems or aircraft control systems as unreliable. Therefore, it is of paramount impor...

Claims

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Application Information

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IPC IPC(8): G11C29/00G11C29/02
CPCG11C29/02G11C29/024G11C29/028G11C29/04G11C29/56
Inventor M·阿兹曼A·K·马希
Owner NXP BV
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