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Bistable multi-resonant circuit

A multivibrator, bistable technology, applied in static memory, instruments, electrical components, etc., can solve the problem of increasing the circuit scale, such as the transmission gate transistor 108

Inactive Publication Date: 2006-09-13
SANYO ELECTRIC CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Accordingly, in the conventional example of the flip-flop circuit 101, there is a problem that the circuit scale is increased by the part of the transfer gate transistor 108.

Method used

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  • Bistable multi-resonant circuit
  • Bistable multi-resonant circuit
  • Bistable multi-resonant circuit

Examples

Experimental program
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Effect test

Embodiment 1

[0043] First, refer to figure 1 The circuit configuration of the shift register circuit using the flip-flop circuit according to the first embodiment will be described.

[0044] The shift register circuit of the embodiment 1 is as figure 1 As shown, it consists of a multi-stage bistable multivibrator circuit 1 connected in series. In addition, the multistage flip-flop circuit is constituted by two stages of delay latch circuits 2a and 2b, respectively. In addition, these delay latch circuits 2a and 2b are examples of the "first latch circuit" and the "second latch circuit" of the present invention, respectively. A given input signal is input from the node D to the delay gate circuit 2a of the first stage, and after the given input signal is locked for a certain period of time, an inverted phase of the given input signal is output to the delay gate circuit 2b of the second stage. Signal. In addition, the output signal from the delay gate circuit 2a of the first stage is i...

Embodiment 2

[0086] Refer below Figure 8 The structure of the DRAM using the shift register circuit including the flip-flop circuit according to the second embodiment will be described.

[0087] The DRAM of embodiment 2 such as Figure 8As shown, memory cell 21 provided at the intersection of word line WL and bit line BL1, shift register circuit 22, and n-channel transistors 23a and 23b are included. The memory cell 21 is composed of an n-channel transistor 21a and a capacitor 21b. In addition, the gate of n-channel transistor 21a is connected to word line WL. In addition, the capacitor 21 b holds charges corresponding to data stored in the memory unit 21 . In addition, the n-channel transistors 23 a and 23 b are respectively connected so that one of the source / drain regions is connected to the bit lines BL1 and BL2 , and the other is connected to the shift register circuit 22 .

[0088] The shift register circuit 22 is composed of a plurality of flip-flop circuits 31 connected in ser...

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PUM

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Abstract

A flip-flop circuit capable of inhibiting current consumption as well as the circuit scale from increase is provided. This flip-flop circuit comprises a first latch circuit including first and second inverter circuits. A first power supply line capable of switching a supplied potential between a fixing potential supplied for fixing the potentials of output nodes of the first and second inverter circuits and a floating potential supplied for floating the potentials of the output nodes of the first and second inverter circuits is connected to the first latch circuit.

Description

technical field [0001] The present invention relates to a bistable multivibrator circuit, and more particularly to a bistable multivibrator circuit including a latch circuit. Background technique [0002] There are flip-flop circuits including various latch circuits in the prior art. Such a flip-flop circuit is described, for example, in JP-A-8-279298. [0003] Figure 11 A conventional example of a flip-flop circuit 101 having the same configuration as the flip-flop circuit described in JP-A-8-279298 is shown. Such as Figure 11 As shown, the flip-flop circuit 101 based on this conventional example is composed of two delay latch circuits 102 a and 102 b and one inverter circuit 103 . In addition, the delay latch circuit 102 a of the first stage is composed of a latch circuit 104 and a transfer gate transistor 105 . The latch circuit 104 is composed of two inverter circuits 106 and 107 and a transfer gate transistor 108 . [0004] Furthermore, the output terminal of the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K3/356G11C19/28
CPCG11C19/28H03K3/0372G11C19/00H03K3/012
Inventor 宫本英明
Owner SANYO ELECTRIC CO LTD
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