Method and device for varying an active duty cycle of a wordline

Abstract

A semiconductor memory is provided which is operable in at least a test mode. Such semiconductor memory includes a memory array, the memory array including a plurality of memory cells which are accessible through a plurality of respective wordlines and a plurality of respective bitlines. A row decoder driver is operable to activate one wordline of the plurality of wordlines at a first point in time that is determined in relation to a first signal and to deactivate the wordline at a second point in time that is determined in relation to a second signal. The semiconductor memory further includes a precharge circuit which is operable to precharge the bitline at a third point in time, the third point in time occurring no sooner than the second point in time. A variable length delay circuit is operable to output the second signal at a delayed timing after the first signal and delayed in relation to the first signal, the delayed timing having a controllably variable length.

Description

technical field [0001] The present invention relates to semiconductor integrated circuits and their testing. Background technique [0002] Production testing of semiconductor integrated circuits, also referred to herein as "chips", requires not only devices that cannot be reliably identified and processed but also devices that operate on the margins, ie devices whose operation is close to failure. Typically to avoid a later failure of the fringe device (which may then require more expensive repairs), the fringe device is taken off-line and replaced by a device that has tested good. Alternatively, an edge device may be allowed to retain a portion of the operating configuration provided the chip is properly labeled and confirms the device's marginality to downstream users who incorporate the edge chip into other equipment. In other words, some chips operate satisfactorily under certain limited conditions, such as in less frequent use, for shorter durations, for shorter on-tim...

AI Technical Summary

Problems solved by technology

However, as becomes apparent from the following, there is the following problem: making the PCHG transform at the required time needs to face formidable difficulties

The transition time tT and the jitter tJ make the signal edge and duration of the WL_EN signal imprecise

However for the write-window test it is necessary to change the word line activation interval tW of 1 ns to the range of 20 to 30 ns, the large jitter and long transition time of the prior art device shown in Figure 1 precludes performing such a test

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