Flash memory loading method and system based on boundary scan

A boundary scan and flash memory technology, which is applied in the direction of program loading/starting, information storage, static memory, etc., can solve the problem of incompatibility between loading speed and loading resources occupied by loading, loading stability, etc., to improve transmission efficiency and loading speed, Effect of reducing the number of times data is transferred

Active Publication Date: 2006-10-11
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0020] The invention provides a boundary scan bridge, a loading system and a loading method to solve the problem that the current loading speed, resources occupied by loading, and loading stability cannot be achieved at the same time

Method used

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  • Flash memory loading method and system based on boundary scan
  • Flash memory loading method and system based on boundary scan
  • Flash memory loading method and system based on boundary scan

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0055] Example 1 of the bridge: the bridge has a sufficient number of IO interfaces (that is, enough to meet the number requirements of address lines and data lines of the flash memory).

[0056] see image 3 As shown, the bridge includes: a JTAG bus interface, an IO interface, and a control signal generation module and a status signal reading module respectively connected to the JTAG bus interface and the IO interface.

[0057] The JTAG bus interface connects the bridge to the JTAG bus.

[0058] IO interface, used to exchange data with external flash memory.

[0059] The control signal generation module is used to receive instructions from the JTAG bus through the JTAG bus interface, generate control signals correspondingly according to the instructions, and output them through the IO interface.

[0060] The state signal reading module is used to receive the instructions sent by the JTAG bus through the JTAG bus interface, and read the corresponding state signal of the exte...

example 2

[0070] System Example 2: The bridge does not have a sufficient number of IO interfaces (that is, insufficient to meet the requirements for the number of address lines and data lines of the flash memory).

[0071] see Image 6 As shown, the system includes: JTAG bus, JTAGTBC and JTAG Bridge connected with the JTAG bus, and the flash memory to be loaded connected with the JTAG Bridge; the flash memory to be loaded is also connected with the CPU or logic device Connected to the above JTAG Bridge.

[0072] The flash memory to be loaded includes: a data read-write interface, an address read-write interface, a control signal input interface and a state signal output interface. Because the IO interface quantity of JTAG Bridge is insufficient in this example, so this example also includes: CPU or logic device, it is connected with the data read-write interface and the address read-write interface of the flash memory to be loaded, and through TAP interface and described The JTAG Brid...

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PUM

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Abstract

The invention discloses a boundary scan bridge, a load system and relative method, which can solve the problems that the load speed, load resource and load stability can not be both best. The inventive load system comprises: a boundary scan bus; a boundary scan test bus controller that connected to said boundary scan bus; loaded memory; and a boundary scan bridge, which is connected to the loaded memory via internal IO interface and connected to the JTAG bus.

Description

technical field [0001] The invention relates to the field of boundary scan, in particular to a boundary scan-based flash memory loading method, a boundary scan bridge and a boundary scan based flash memory loading system. Background technique [0002] Currently, there are two main types of flash memory loading systems based on boundary scan (JTAG). [0003] Prior art one: conventional methods. [0004] see figure 1 As shown, directly connect the data lines, address lines, control lines (read / write / enable, etc.) and status lines (ready / busy, etc.) of the flash memory on the board to the CPU or logic device of the board, The CPU or the logic device is connected to the JTAG Bridge through the TAP interface, and the JTAG Bridge is connected to the JTAG TBC through the JTAG bus (the bus meeting the IEEE1149.1 technical specification). [0005] The loading of the flash memory described in this loading method does not depend on the software run by the CPU or logic device of the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F3/06G06F9/445G11C16/10
Inventor 张玉
Owner HUAWEI TECH CO LTD
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