Semiconductor memory having charge trapping memory cells and fabrication method thereof

Abstract

A semiconductor memory having charge trapping memory cells, where the direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.

Description

technical field [0001] The present invention relates to the field of electrically writable and erasable non-volatile flash memory. In particular, it teaches a non-volatile memory having a charge trapping cell comprising a trapping dielectric which is especially suitable for virtual grounded NOR memory cell structures. Background technique [0002] Charge-trapping semiconductor memories typically have an array of charge-trapping memory cells arranged in columns and rows, where each memory cell is constructed as a transistor comprising a gate dielectric typically sandwiched between two boundary layers The charge-trapping storage layer between them is composed. Typically, the storage layer material has a smaller energy bandgap and a larger trap density than the boundary layer material, so that the charge carriers trapped in the storage layer remain localized. Typically, nitrides are used as memory layer materials, while oxides are used as boundary layer materials. Depending ...

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Problems solved by technology

More specifically, scaling down the memory cell will result in increasingly shorter lengths of the channel region, i.e., the area spacing between the source / drain regions, making breakdown of the memory cell more likely

In addition, memory cells using multi-bit memory modes that essentially require localized charge distributions on the drain and source sides of the memory cell's storage layer may result in undesired superimposition of charge distributions, preventing clear distinction of logic states

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