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Semiconducter device and mfg. method thereof

A manufacturing method, semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, transistors, etc., can solve problems such as difficult to form openings with high aspect ratios, undisclosed, and difficult

Inactive Publication Date: 2006-11-15
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, problems such as deterioration of the step coverage of the upper electrode, difficulty in forming an opening with a high aspect ratio, more difficulty in the case of forming an opening in a laminated film, etc. occur, for example.
[0021] However, in the second conventional example, there is no disclosure of an example in which a structure in which the potential extraction portion of the upper electrode is connected to the diffusion layer through the opening of the ferroelectric film is applied to a ferroelectric memory element of a three-dimensional stack type structure. , Used in a structure in which a ferroelectric capacitor is covered with a hydrogen barrier film

Method used

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  • Semiconducter device and mfg. method thereof
  • Semiconducter device and mfg. method thereof
  • Semiconducter device and mfg. method thereof

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Embodiment Construction

[0082] Hereinafter, various embodiments of the present invention will be described with reference to the drawings.

[0083] (first embodiment)

[0084] Below, refer to Figure 1 to Figure 7 , the semiconductor device according to the first embodiment of the present invention will be described.

[0085] figure 1 It is a sectional view of the semiconductor device according to the first embodiment of the present invention.

[0086] like figure 1 As shown, an element isolation region (STI) 101 is formed on a semiconductor substrate 100 to divide an element formation region. A first impurity diffusion layer (first conductive layer) 102 and a second impurity diffusion layer (second conductive layer) 103 are provided in the element formation region partitioned by the element isolation region 101 . As a supplementary note, cobalt silicide (CoSi 2 ). In this case, further reduction in resistance can be achieved and delay in circuit operation can be prevented. exist figure 1...

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Abstract

This invention discloses semiconductor device and its preparation method. The device includes the first impurity diffused layer and the second layer that formed on the semiconductor substrate and with space between them, the first layer insulation film, the first contact plug, the second layer insulation film, the first peristome and the wall part formed at the first peristome, the first metal film (bottom electrode) that its bottom part is connected to top part of the first contact plug, ferroelectrics film (capacitor insulating film) and the capacitor component made up by the second metal film (up electrode). The second layer and up electrode are connected to the wall part and the bottom second metal film through the second contact plug. So the structure that up electrode electric potential be extracted to the diffused layer can be realized in dielectric storage component of stereoscopic stack-up structure.

Description

technical field [0001] The present invention relates to a semiconductor device related to a potential extraction structure of an upper electrode in a dielectric memory element and a manufacturing method thereof. Background technique [0002] Started mass production of small-capacity ferroelectric memory elements of 1 to 64kbit using planar and laminated structures, and recently started developing ferroelectric memory elements with a three-dimensional laminated structure, which has a three-dimensional laminated structure The element uses a ferroelectric film not only on the planar part but also on the side part. The ferroelectric storage element with a three-dimensional stacked structure can reduce the unit size and improve the integration by disposing a contact plug electrically connected to the semiconductor substrate directly under the lower electrode; by forming a capacitor insulating film along the steps, the capacity is insulated The surface area of ​​the membrane is i...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/10G11C11/22H10B12/00
Inventor 三河巧十代勇治
Owner PANASONIC CORP