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Memory interface for systems with multiple processors and one memory system

A technology of memory interface and memory controller, applied in the field of memory system

Inactive Publication Date: 2013-03-20
OPTIS WIRELESS TECH LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Other challenges include flushing memory (i.e., the CPU will perform the flush), preventing one CPU from modifying another CPU's data, determining the latency or latency of each CPU, etc.

Method used

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  • Memory interface for systems with multiple processors and one memory system

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Embodiment Construction

[0021]The following is a detailed description of illustrative embodiments of the invention with reference to the drawings, wherein like reference numerals are used for like or similar elements. The term "access" as used herein, when used in conjunction with the term "external memory", means any memory operation including, but not necessarily limited to, read operations, write operations, and refresh operations.

[0022] Although the asynchronous request-grant system works reasonably well, several improvements are still desired. For example, the various handshaking processes that occur between the CPU and the memory interface consume valuable bandwidth. In addition, it is difficult to predict the latency of the system with any accuracy for a given CPU because memory accesses, once granted, are usually not interrupted until that CPU is completed. This unknown and potentially long wait time can cause problems for other CPUs, especially in real-time oriented applications.

[002...

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Abstract

Memory interface for multi-CPU system provides predefined time slots in which each CPU may access an external memory. The time slot assigned to each CPU may be defined according to the expected memory requirements of the CPU. In this way, each CPU is guaranteed to have a certain amount of dedicated bandwidth to the external memory. The predefined time slots also allow the latency of the system to be known, which is useful for real-time oriented applications. Moreover, each CPU may use its own clock during its allotted time slot to control the external memory, thus accommodating various clock domains in the system. Memory refresh and data protection functions are also provided. This Abstract is provided to comply with rules requiring an Abstract that allows a searcher or other reader to quickly ascertain subject matter of the technical disclosure. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Description

[0001] Cross References to Related Applications [0002] This application claims U.S. Provisional Applications from Serial Nos. 60 / 509503, filed October 8, 2003, 60 / 510074, filed October 9, 2003, and 60 / 530960, filed December 19, 2003 priority, which are hereby incorporated by reference. All applications have the title "High Performance and Reliability Memory Interface for Systems with Multiple CPUs and One Memory (for high performance and high reliability memory interface for systems with multiple CPUs and one memory)". technical field [0003] The present invention relates to memory systems, and more particularly to interfaces for memory systems that are accessible by multiple processors. Background technique [0004] A control processor (CPU) requires memory for operation. The memory can be located on the same integrated circuit or "chip" as the CPU, as in the case of digital application-specific integrated circuits (ASICs), or it can be provided externally. On-chip me...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/46G06F13/16G06F9/50G06F12/14
CPCG06F12/1441G06F13/1605G06F9/50G06F9/46
Inventor F·安斯马克T·尼尔松D·巴洛
Owner OPTIS WIRELESS TECH LLC