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A semiconductor device and methods of manufacturing thereof, a semiconductor device structure

A device structure and manufacturing method technology are applied in the field of semiconductor device structure to achieve the effects of reducing etching deviation, improving consistency and improving overall yield

Active Publication Date: 2006-11-22
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, most of these technologies use precious resources and sometimes require correct and unique process control

Method used

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  • A semiconductor device and methods of manufacturing thereof, a semiconductor device structure
  • A semiconductor device and methods of manufacturing thereof, a semiconductor device structure
  • A semiconductor device and methods of manufacturing thereof, a semiconductor device structure

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Embodiment Construction

[0036] The present invention relates to the structure and manufacturing method of semiconductor laminated circuits, and more particularly to the method and structure for reducing the independent-dense bias effect.

[0037] In order to make the purpose, features and advantages of the present invention more comprehensible, preferred embodiments are specifically cited below and described in detail with accompanying drawings. The description of the present invention provides different examples to illustrate the technical features of different implementations of the present invention. Wherein, the configuration of each element in the embodiment is for illustration, not for limiting the present invention. In addition, part of the symbols in the figures in the embodiments are repeated for the purpose of simplifying the description, and do not imply the relationship between different embodiments.

[0038] see figure 2 , which shows a legacy function device. The functional device 2...

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PUM

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Abstract

The present invention provides a semiconductor device, a manufacturing method thereof, and a structure of the semiconductor device. The semiconductor device includes a plurality of layers having functional patterns, and the semiconductor device is at least partially composed of the functional patterns. At least one layer of the plurality of layers further includes a non-functional pattern, wherein the non-functional pattern is adjacent to the functional pattern of the at least one layer to form a combined pattern of the at least one layer, so that the feature density of the combined pattern is higher. average. The non-functional pattern of the semiconductor device, its manufacturing method, and semiconductor device structure described in the present invention can balance functional devices, provide a relatively more consistent element configuration for each device layer, and further improve the consistency of feature dimensions. Moreover, due to the improvement of feature reliability and consistency, etching deviation can also be reduced, thereby improving the overall yield of the device.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a semiconductor device reducing the independent-intensive bias effect, a manufacturing method thereof, and a structure of the semiconductor device. Background technique [0002] As far as an integrated circuit (IC) layout designer is concerned, it is always possible to integrate or densely gate transistors in a specific area of ​​an IC layout, while other areas are used for individual gates. Variations in transistor density in IC design may affect a transistor's feature size or critical dimension during semiconductor processing. In particular, irregular feature sizes may become apparent during lithography, and these irregularities may be amplified during subsequent deposition or etch processes. In other words, even with the same design in a layout, the lithography and etching results of a dense population of transistors may not be the same as individual transistors. [0...

Claims

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Application Information

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IPC IPC(8): H01L27/02H01L21/768H01L21/82H01L23/528
CPCG03F1/36H01L27/0207H01L27/118H10B69/00
Inventor 田丽钧张弥彰林晃生韩郁琪
Owner TAIWAN SEMICON MFG CO LTD