Memory controller
A technology of memory controller and memory area, which is applied in the direction of instruments, electrical digital data processing, etc., can solve the problem of high cost, and achieve the effect of high data throughput
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[0024] figure 2 The SDRAM controller 1 used in a system with three channels is used as an example to show a block diagram of the memory controller of the present invention. The system is: via the AMBA bus 8 and input 6 and output 7 for real-time data streaming And the connected CPU. Each bank 21, 22, 23, 24 in the SDRAM module 2 has an associated state machine 41, 42, 43, 44 in the bank control unit 4, which describes the bank 21, 22 , 23, and 24, and are responsible for observing the waiting time and the correct state sequence. These state machines 41, 42, 43, 44 send their commands for the banks 21, 22, 23, 24 to the command scheduler 3 (command bus scheduler). The command scheduler 3 monitors the distribution of external commands and data buses. In each clock cycle, the command scheduler 3 sends a command selected according to the priority to the DRAM module 2. The state machines 41, 42, 43, 44 directly obtain their transfer commands from the three channels (input 6, AMBA 8, ...
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