Hardware alternative technique based computer data sampling method and system

Abstract

The disclosed computer data acquirement method based on hardware alternative technology comprises: arranging two data acquirement cards every with at least three A / D channels (CH1-CH3); dividing target signal into two ways to send to the CH1 channel of two cards; connecting with different external trigger signal T1 and T2 to the CH2 channel of last two cards; besides, dividing the positioning pulse signal D generated by external trigger and time-sequence system into two ways for the CH3 channel. This invention can work stably for long time, and ensures data accuracy and integration.

Description

technical field

[0001] The invention relates to a computer data collection method and system, in particular to a computer data collection method and system based on hardware alternate technology. Background technique

[0002] The main parameters to measure the efficiency of computer data acquisition system mainly include: channel sampling rate (KS / S), continuous acquisition time (S) and data acquisition accuracy (BIT). At present, most common data acquisition systems use on-board high-speed cache for data acquisition and storage. In this way, the data is directly stored in the high-speed cache of the acquisition card itself during the acquisition process, which can realize the high-speed data acquisition process. However, due to the limitation of onboard cache capacity and hardware cost, if a data acquisition system using this method needs to collect data for a long time, it can only be at the expense of channel sampling speed. Therefore, its application is also subject to...

Examples

Embodiment Construction

[0014] Such as figure 1 As shown, each original signal to be collected is divided into two channels, which are respectively sent to the CH1 channels of the two acquisition cards, and the CH2 channels of the two acquisition cards are respectively connected to different external trigger logics T1 and T2. When T1 is triggered, one CH1 channel performs A / D conversion and saves the data to the onboard cache; similarly, when T2 is triggered, the signal enters another CH1 channel for A / D conversion and storage. The acquisition time length Ta of the CH1 A / D channels on the two acquisition cards after each trigger arrival is determined by the onboard buffer capacity and channel sampling frequency, and during the alternate trigger acquisition process of the two CH1 channels, it is necessary to control T1 and The timing logic of the two trigger signals of T2 ensures that the data collected alternately by the two channels has a certain overlapping area Ts. The timing of the two acquisiti...

technical field

[0001] The invention relates to a computer data collection method and system, in particular to a computer data collection method and system based on hardware alternate technology. Background technique

[0002] The main parameters to measure the efficiency of computer data acquisition system mainly include: channel sampling rate (KS / S), continuous acquisition time (S) and data acquisition accuracy (BIT). At present, most common data acquisition systems use on-board high-speed cache for data acquisition and storage. In this way, the data is directly stored in the high-speed cache of the acquisition card itself during the acquisition process, which can realize the high-speed data acquisition process. However, due to the limitation of onboard cache capacity and hardware cost, if a data acquisition system using this method needs to collect data for a long time, it can only be at the expense of channel sampling speed. Therefore, its application is also subject to...

Examples

Embodiment Construction

[0014] Such as figure 1 As shown, each original signal to be collected is divided into two channels, which are respectively sent to the CH1 channels of the two acquisition cards, and the CH2 channels of the two acquisition cards are respectively connected to different external trigger logics T1 and T2. When T1 is triggered, one CH1 channel performs A / D conversion and saves the data to the onboard cache; similarly, when T2 is triggered, the signal enters another CH1 channel for A / D conversion and storage. The acquisition time length Ta of the CH1 A / D channels on the two acquisition cards after each trigger arrival is determined by the onboard buffer capacity and channel sampling frequency, and during the alternate trigger acquisition process of the two CH1 channels, it is necessary to control T1 and The timing logic of the two trigger signals of T2 ensures that the data collected alternately by the two channels has a certain overlapping area Ts. The timing of the two acquisiti...

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