Stack cache memory applied for context switch and buffer storage method

Abstract

This invention discloses one shed high buffer memory and its buffer memory method suitable for upper and down text switch, which comprises at least two shed high speed buffer blocks; one or gate circuit, one selector, wherein, the shed buffer memory block is composed of label part, data part and control part; the said shed high speed buffer block is composed of at least three comparing circuits and one and gate circuit. The method comprises the following steps: a, initiating shed; b, aligning shed space; c, recycling shed space; comparing label to determine whether to shot of shed high buffer.

Description

technical field [0001] The invention relates to the technical field of microprocessor architecture, in particular to a stack cache memory and a buffer storage method suitable for context switching. Background technique [0002] With the rapid development of microprocessor design and production technology, the gap between memory access speed and processor operation speed is becoming more and more significant. Moreover, the gap between the access speed of the memory and the operation speed of the processor increases at a rate of 50% every year, making the memory access speed more and more a bottleneck for improving the performance of the processor. Utilizing the principle of locality, using one or more levels of cache memory (Cache, referred to as "cache") is one of the effective means to improve the performance of the storage system. A cache is a small, fast special memory that holds instructions and data recently used by the processor. When the processor is running, if the...

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Problems solved by technology

Therefore, a processor with a stack cache has good performance in a single-process application, but the effect is not ideal when running in a multi-process (including thread) environment, especially when context switching is frequent

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