Semiconductor device package and method of manufacturing the same
a semiconductor device and semiconductor technology, applied in the direction of microstructured devices, microstructured devices, testing/measurement of semiconductor/solid-state devices, etc., can solve the problems of semiconductor devices tilting, adversely affecting the performance of semiconductor device packages, and difficult control of bl
Active Publication Date: 2020-06-23
ADVANCED SEMICON ENG INC
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- Abstract
- Description
- Claims
- Application Information
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Problems solved by technology
It is challenging to control BLT due to various manufacturing conditions (e.g. error or deviation resulted from machine(s) used to attach or bond the semiconductor device to the carrier, characteristic of the adhesive material, etc.).
However, the adhesive material may bleed or flow into the hole to adversely affect the performance of the semiconductor device package.
Further, the semiconductor device's center of gravity may not overlap with its geometric center, which may cause the semiconductor device to tilt when (or subsequent) to placing the semiconductor device to the adhesive material.
Tilt of the semiconductor device may also adversely affect the performance of the semiconductor device package.
Method used
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Embodiment Construction
[0018]FIG. 1A illustrates a semiconductor device package 1 in accordance with some embodiments of the present disclosure. The semiconductor device package 1 includes a substrate 10, a MEMS device 11 (or abbreviated as MEMS 11) and an adhesive 12.
[0019]The substrate 10 may be, for example, a printed circuit board (PCB), such as a paper-based copper foil laminate, a composite copper foil laminate, a polymer-impregnated glass-fiber-based copper foil laminate, or a combination of two or more thereof. The substrate 10 may include an interconnection structure, such as a redistribution layer (RDL) or a grounding element. The substrate 10 may include a through via 10v penetrating the substrate 10 to provide an electrical connection between a surface 101 (also referred to as a top surface or a first surface) of the substrate 10 and a surface 102 (also referred to as a bottom surface or a second surface) of the substrate. The substrate 10 defines an opening (or a gap) 10h penetrating the subs...
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Abstract
The present disclosure relates to a semiconductor device package. The semiconductor device package includes a substrate, a support structure, an electronic component and an adhesive. The support structure is disposed on the substrate. The electronic component is disposed on the support structure. The adhesive is disposed between the substrate and the electronic component and covers the support structure. A hardness of the support structure is less than a hardness of the electronic component.
Description
CROSS-REFERENCE TO RELATED APPLICATION[0001]This application claims the benefit of and priority to U.S. Provisional Application No. 62 / 472,431, filed Mar. 16, 2017, the content of which is incorporated herein by reference in its entirety.BACKGROUND1. Technical Field[0002]The present disclosure relates to a semiconductor device package, more particularly, to a semiconductor device package including a substrate with a support element and method of manufacturing the same.2. Description of the Related Art[0003]A semiconductor device package may include a semiconductor device which is attached or bonded to a carrier (a substrate, a leadframe or the like) by an adhesive material. The bond line thickness (BLT) or thickness of the adhesive material is one of the factors that may affect performance of the semiconductor device package. It is challenging to control BLT due to various manufacturing conditions (e.g. error or deviation resulted from machine(s) used to attach or bond the semicondu...
Claims
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IPC IPC(8): B81B7/00B81C1/00B81B3/00H01L23/31H01L23/13H01L23/28H01L23/12H01L23/538H01L23/48H01L23/522H01L23/52H01L23/525H01L21/66B81C3/00
CPCH01L23/5226H01L22/22H01L23/525H01L23/481H01L23/13B81C1/00658H01L23/52H01L23/5382H01L23/5386H01L23/31B81C3/001B81B7/0061H01L23/3157B81B3/007H01L23/12H01L23/28B81C2203/032B81B2203/0127B81B2207/07B81C2201/0156B81B7/0032B81B7/0058B81C1/00261H01L2924/15151H01L2924/10155H01L2224/48091H01L2224/73265H01L2224/73204H01L2224/73257H01L2924/00014
Inventor LEE, MING YENSUNG, CHIA HAOHUANG, CHING-HANTSAI, YU-HSUAN
Owner ADVANCED SEMICON ENG INC