Nanoscale patterning for the formation of extensive wires

Abstract

A method for forming a platen useful for forming nanoscale wires for device applications comprises: (a) providing a substrate having a major surface; (b) forming a plurality of alternating layers of two dissimilar materials on the substrate to form a stack having a major surface parallel to that of the substrate; (c) cleaving the stack normal to its major surface to expose the plurality of alternating layers; and (d) etching the exposed plurality of alternating layers to a chosen depth using an etchant that etches one material at a different rate than the other material to thereby provide the surface with extensive strips of indentations and form the platen useful for molding masters for nano-imprinting technology. The pattern of the platen is then imprinted into a substrate comprising a softer material to form a negative of the pattern, which is then used in further processing to form nanowires. The nanoscale platen thus comprises a plurality of alternating layers of the two dissimilar materials, with the layers of one material etched relative the layers of the other material to form indentations of the one material. The platen is then oriented such that the indentations are parallel to a surface to be imprinted.

Description

[0001] The present application is related to application Ser. No. 09 / 280,048, entitled "Chemically Synthesized and Assembled Electronic Devices", filed on Mar. 29, 1999, which is directed to the formation of nanowires used for nanoscale computing and memory circuits. The present application is also related to applications Ser. No. 09 / 280,225, entitled "Molecular Wire Crossbar Interconnect (MWCI) for Signal Routing and Communications", Ser. No. 09 / 280,045, entitled "Molecular Wire Crossbar Logic (MWCL)", Ser. No. 09 / 280,189, entitled "Molecular Wire Crossbar Memory", and Ser. No. 09 / 280,188, entitled "Molecular Wire Transistor (MWT)", all also filed on Mar. 29, 1999, which are all directed to various aspects of memory and logic circuits utilized in nanocomputing.[0002] The present invention is generally directed to nanoscale computing and memory circuits, and, more particularly, to the formation of nanowires for device applications.[0003] With the constantly decreasing feature sizes ...

AI Technical Summary

Problems solved by technology

With the constantly decreasing feature sizes of integrated-circuit devices, the need for increasingly fine, lithographically-defined patterning is limiting further advances of the technology.

However, Au and Fe migrate into Si rapidly and create deep levels, which can degrade devices, such as addressing circuitry and other portions of the system formed by conventional Si integrated-circuit technology.

However, it is difficult to control the placement of these free-standing wires, and therefore it is difficult to use these nanowires in real integrated circuits.

Also, the use of X-rays requires a synchrotron, and thus is very expensive.

In either event, it is not presently possible to achieve critical dimensions in patterning down to 10 nm.

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