Semiconductor memory device and method of reading data from the semiconductor memory device

Abstract

A semiconductor memory device and method of reading data from the semiconductor memory device is described. The semiconductor memory device may generate a data read clock signal that changes from a first logic state to a second logic state, and may read out bit cell data from a plurality of bit lines based on the generated data read clock signal. A word line signal and a dummy word line signal may be activated from the first logic state to the second logic state based on incoming X-address signals and Y-address signals. An enable signal may be output based on the activated dummy word signal, and a sense amplifier may sense the read-out bit cell data and a reference signal based on the activated enable signal, and output a corresponding to the sensed read-out bit cell data.

Description

PRIORITY STATEMENT[0001] This application claims the priority of Korean Patent Application No. 2003-39353, filed on Jun. 18, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.[0002] 1. Field of the Invention[0003] The present invention relates to a semiconductor memory device, and a method of reading data from the semiconductor memory device.[0004] 2. Description of the Related Art[0005] FIG. 1 is a circuit diagram of a cell array structure of a conventional ROM. The conventional ROM has a capacity of 1M (1024.times.1024). The conventional ROM of FIG. 1 includes a bit cell array unit 110, a reference cell array unit 120 and a bit cell replica array unit 130, and is disclosed in U.S. Pat. No. 6,404,666.[0006] In FIG. 1, the bit cells M0 to M15 (represented by transistors) of bit cell array unit 110 store bit cell information, i.e., store either logic low data "0" or logic high data "1" depending on whether th...

AI Technical Summary

Problems solved by technology

These process variations in the transistors of the reference cell array unit 120 has an adverse effect on errors generated during or upon a data reading operation.

In other words, if the transistors of the reference cell array unit 120 provide poor uniformity, the reference signals become unstable, and accordingly, the sense amplifier cannot perform a proper comparison with respect to the data stored in the bit cells.

Therefore, the error rate of read-out data increases.

Further, process variations in the transistors of the bit cell replica array unit 130 destabilize the generation of the enable signal for the sense amplifier, thus greatly affecting the error rate of read-out data.

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