Enhanced die-up ball grid array and method for making the same

a grid array and die-up ball technology, applied in semiconductor devices, semiconductor/solid-state device details, electrical devices, etc., can solve the problems of reducing the thermal connection between the ic die and the edge of the stiffener, reducing the reliability requirements of die sizes larger than 9 mm, and high thermal stress of conventional bga packages

Inactive Publication Date: 2005-02-10
AVAGO TECH WIRELESS IP SINGAPORE PTE
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Conventional BGA packages are subject to high thermal stresses that result from the heat given off during operation of the mounted IC die.
As a result, conventional flex BGA packages have difficulty in meeting reliability requirements for die sizes larger than 9 mm.
However, the openings on the stiffener for wire bond connections tend to reduce the thermal connections between the IC die and the edges of the stiffener.
As a result, heat spreading is limited largely to the region of the IC die attach pad, while areas at the stiffener peripheral do not contribute effe

Method used

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  • Enhanced die-up ball grid array and method for making the same
  • Enhanced die-up ball grid array and method for making the same
  • Enhanced die-up ball grid array and method for making the same

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Embodiment Construction

[0049] Overview

[0050] The present invention is directed to a method and system for improving the mechanical, thermal, and electrical performance of BGA packages. The present invention is applicable to all types of BGA substrates, including ceramic, plastic, and tape (flex) BGA packages. Furthermore the present invention is applicable to die-up (cavity-up) and die-down (cavity-down) orientations.

[0051] Numerous embodiments of the present invention are presented herein. In a first embodiment, BGA package thermal stress at the IC die / stiffener interface is released or altered with the introduction of a heat spreader on the top surface of the IC die, enabling large size dies with high input and output (I / O) counts to be packaged using BGA technology. In a second embodiment, BGA package thermal resistance and the length of the current return path are reduced by introducing thermal / ground balls underneath or within close proximity of the IC die. In a third embodiment, the package therma...

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PUM

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Abstract

An electrically and thermally enhanced die-up tape substrate ball grid array (BGA) package and die-up plastic substrate BGA package are described. A substrate that has a first surface and a second surface is provided. The stiffener has a first surface and a second surface. The second stiffener surface is attached to the first substrate surface. An IC die has a first surface and a second surface. The first IC die surface is mounted to the first stiffener surface. A plurality of solder balls is attached to the second substrate surface. In one aspect, a heat spreader is mounted to the second IC die surface. In another aspect, the stiffener is coupled to ground to act as a ground plane. In another aspect, the substrate has a window opening that exposes a portion of the second stiffener surface. The exposed portion of the second stiffener surface is configured to be coupled to a printed circuit board (PCB). In another aspect, a metal ring is attached to the first stiffener surface. In another aspect, wire bond openings in the stiffener are bridged by one or more studs.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The invention relates generally to the field of integrated circuit (IC) device packaging technology, and more particularly to substrate stiffening and heat spreading techniques in ball grid array (BGA) packages. [0003] 2. Related Art [0004] Integrated circuit (IC) dies are typically mounted in or on a package that is attached to a printed circuit board (PCB). One such type of IC die package is a ball grid array (BGA) package. BGA packages provide for smaller footprints than many other package solutions available today. A BGA package has an array of solder balls located on a bottom external surface of a package substrate. The solder balls are reflowed to attach the package to the PCB. The IC die is mounted to a top surface of the package substrate. Wire bonds typically couple signals in the IC die to the substrate. The substrate has internal routing which electrically couples the IC die signals to the solder balls on...

Claims

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Application Information

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IPC IPC(8): H01L23/373H01L23/433
CPCH01L23/3677H01L2224/73265H01L23/4334H01L23/49816H01L23/49838H01L23/50H01L23/562H01L2224/48227H01L2224/48228H01L2224/48237H01L2224/48465H01L2224/49109H01L2224/49171H01L2924/01013H01L2924/01029H01L2924/01039H01L2924/01046H01L2924/01078H01L2924/01079H01L2924/1433H01L2924/15153H01L2924/15165H01L2924/15311H01L2924/19041H01L2924/30107H01L24/48H01L24/49H01L2224/32225H01L2224/73215H01L23/3735H01L2924/00H01L2924/00012H01L2924/351H01L2924/15787H01L2924/181H01L2224/45144H01L24/45H01L2924/14H01L2224/2929H01L2224/29339H01L2224/32245H01L2224/33181H01L2224/05624H01L2224/8385H01L2924/00014H01L2924/0665H01L23/34H01L23/5384H01L24/14
Inventor KHAN, REZA-UR R.ZHAO, SAM Z.BACHER, BRENT
Owner AVAGO TECH WIRELESS IP SINGAPORE PTE
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