Cache memory and method for handling effects of external snoops colliding with in-flight operations internally to the cache

Abstract

A cache memory that completes an in-flight operation with another cache that collides with a snoop operation, rather than canceling the in-flight operation. Operations to the cache comprise a query pass and one or more finish passes. When the cache detects a snoop query intervening between the query pass and a finish pass of the in-flight operation, the cache generates a more up-to-date status for the snoop query that takes into account the tag status to which the in-flight finish pass will update the implicated cache line. This is necessary because otherwise the snoop query might not see the affect of the in-flight finish pass status update. This allows the in-flight finish pass to complete instead of being cancelled and the snoop finish pass to correctly update the status after the in-flight finish pass, and to provide modified data from the cache line to the externally snooped transaction.

Description

[0001] This application claims priority based on U.S. Provisional Application, Serial No. 60 / 375469, filed Apr. 24, 2002, entitled METHOD FOR HANDLING AFFECTS OF EXTERNAL SNOOPS INTERNALLY TO L2 CACHE.FIELD OF THE INVENTION [0002] This invention relates in general to the field of cache memories in microprocessors, and particularly to multi-pass pipelined caches and the effects of external snoop operations thereon. BACKGROUND OF THE INVENTION [0003] Many modern computer systems are multi-processor systems. That is, they include multiple processors coupled together on a common bus that share the computing load of the system. In addition, the multiple processors typically share a common system memory. Still further, each of the processors includes a cache memory, or typically a hierarchy of cache memories. [0004] A cache memory, or cache, is a memory internal to the processor that stores a subset of the data in the system memory and is typically much smaller than the system memory. Tra...

AI Technical Summary

Benefits of technology

[0021] An advantage of the present invention is that the cache advantageously keeps the results of the snoop collision completely contained within itself. This potentially improves processor cycle timing, particularly by eliminating the problems associated with inter-cache communications across the processor integrated circuit previously needed by the conventional approach to handle a cancellation of an in-flight operation whose address collided with an external snoop operation. Additionally, it reduces the complexity of other caches in the processor that initiate the in-flight operation.

[0022] Other features and advantages of the present invention will become apparent upon study of the remaining portions of the specification and drawings.

Problems solved by technology

The presence of multiple processors each having its own cache that caches data from a shared memory introduces a problem of cache coherence.

A colliding snoop while the castout is in-flight introduces significant design problems that must be addressed.

However, this approach has negative side effects.

It increases the timing and complexity of the cache control logic to be able to handle the cancelled in-flight operation.

The longer the L1 must wait to overwrite the castout line, the more complicated the process to back out and / or retry the operation.

Also, the added delay may adversely affect performance.

Furthermore, the added communication between the caches in the form of cancellation and handshaking may take place on signals between the two caches that are relatively long and have significant propagation delay if the two cache blocks are a relatively great distance from one another, which may consequently create critical timing paths.

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