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Methods for establishing electrical connections by drawing one or both of an element of an electrical connector and a contact toward the other

a technology of electrical connectors and electrical connections, applied in the field of methods and apparatus, can solve the problems of unreliable semiconductor devices sold and used, failure of semiconductor devices, damage to wafers, etc., and achieve the effect of decreasing increasing the temperature of semiconductor devices

Inactive Publication Date: 2006-08-31
LADD JOHN W
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

"The present invention provides an electrical connector and methods for stress testing semiconductor devices. The connector applies an electrical connection to a semiconductor device without damaging the device. The connector has two members that apply force to the device in opposite directions, creating an equal and opposite force. The connector can be positioned non-rigidly against the device using magnets or other attractive elements. The stress testing method involves non-rigidly securing the connectors to a ground and power source, and exposing the device to temperature variations. The technical effects of the invention include reducing the risk of damage to semiconductor devices during stress testing and improving the accuracy of the testing process."

Problems solved by technology

For example, about 10 milliamps (mA) of current may be applied to each semiconductor device carried upon a substrate as the temperature of the semiconductor device is cycled between ambient temperature and a temperature of at least about 100° C. Such cycling of the temperature of the semiconductor device as current is being applied thereto is intended to stress the semiconductor device by driving any contaminants therein into the active circuitry thereof, thus causing failure of the semiconductor device.
This type of stress testing is known in the art to cause the early failure of unreliable semiconductor devices, thereby preventing these unreliable semiconductor devices from being sold and used.
As a result, a large amount of pressure may be applied to a small area on the wafer, which may cause damage to the wafer that may, in turn, damage semiconductor devices carried by the wafer.
In addition, as the temperature of the burn-in oven is increased, the alligator clips may expand and, thus, be moved along the wafer, which may also damage the wafer, as well as the semiconductor devices formed thereon.
While C-clamps contact larger areas of the respective common ground and power (VCC) contacts formed on the active surface of a wafer, as well as larger areas on the backside of the wafer, and apply force to the wafer in a direction substantially normal, or perpendicular, to the plane of the wafer, C-clamps are relatively clumsy and would, therefore, likely increase the chance that a wafer is damaged as C-clamps are secured to their respective contacts.
Moreover, when stress testing involves varied temperatures, the expansion of a C-clamp would increase the amount of force applied to the wafer, which could crack or otherwise damage the wafer, as well as semiconductor devices carried upon the wafer.
Conversely, contraction of a C-clamp during cooling could result in an inadequate electrical connection between the C-clamp and its corresponding contact.
Thus, the amount of power and voltage applied to each die during wafer-level burn-in testing may not be consistent or repeatable when alligator clips or C-clamps are used to supply a burn-in voltage to dice through a common contact on the wafer or other substrate.
No known apparatus or method for establishing an electrical contact with a common contact on a wafer is available which does not induce stress on or in the wafer.
No known apparatus or method in wafer-scale stress testing of semiconductor devices is available without applying too much force or too little force to the wafer.

Method used

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  • Methods for establishing electrical connections by drawing one or both of an element of an electrical connector and a contact toward the other
  • Methods for establishing electrical connections by drawing one or both of an element of an electrical connector and a contact toward the other
  • Methods for establishing electrical connections by drawing one or both of an element of an electrical connector and a contact toward the other

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Embodiment Construction

[0025] A semiconductor wafer, referred to herein as a substrate 10, which includes a plurality of semiconductor devices 14 carried upon an active surface 11 thereof, is illustrated in FIG. 1. Substrate 10 also includes, on active surface 11, a common ground contact 16 and a common power (VCC) contact 18. Common ground contact 16 and common power (VCC) contact 18 both communicate with a number of different semiconductor devices 14 on substrate 10 by way of respective circuit traces 17, 19 carried upon active surface 11 of substrate 10. Although substrate 10 is illustrated in FIG. 1 as a semiconductor wafer, the hereinafter described electrical connector of the present invention may be used with other substrates, including, without limitation, individual semiconductor dice, full or partial wafers formed of semiconductive material (e.g., silicon, gallium arsenide, iridium phosphide, etc.), and silicon-on-insulator (SOI) substrates, such as silicon-on-glass (SOG), silicon-on-sapphire (S...

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Abstract

A method for establishing an electrical connection includes drawing at least one of a member of an electrical connector and a contact in communication with at least one device. The drawing may be affected nonrigidly. It may occur in a direction substantially normal to a plane of the semiconductor device. Attractive forces, such as magnetic attraction, may cause the drawing. The establishment of electrical connection in this manner may be used in stress testing of semiconductor devices or to otherwise establish an electrical connection between one or more semiconductor devices and a ground, or power source.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation of application Ser. No. 10 / 035,738, filed Nov. 7, 2001, pending, which is a continuation of application Ser. No. 09 / 777,986, filed Feb. 6, 2001, now U.S. Pat. No. 6,340,302, issued Jan. 22, 2002.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to methods and apparatus for effecting wafer-level bum-in, or stress testing, of semiconductor devices and, more particularly, to apparatus and methods for establishing an electrical connection between semiconductor devices on a wafer or other substrate including multiple semiconductor devices thereon and bum-in test equipment. Specifically, the present invention relates to apparatus and methods that employ a magnetic field to establish an electrical connection between semiconductor devices carried upon a wafer or other substrate and burn-in test equipment. [0004] 2. Background of the Related Art [0005] Once semico...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01R43/16G01L1/00G01R1/04G01R31/28
CPCG01R1/0416G01R31/2831G01R31/2863G01R31/3025H01R13/22H01R13/6205Y10T29/49174Y10T29/49169Y10T29/49204Y10T29/49126Y10T29/49004Y10T29/4913H01R2201/20
Inventor LADD, JOHN W.
Owner LADD JOHN W