Semiconductor device and method for manufacturing same

Abstract

The present semiconductor device comprises pillar layers formed on a first semiconductor layer, the pillar layers comprising a first semiconductor pillar layer of a first conductivity type and a second semiconductor pillar layer of a second conductivity type which are alternately formed in a first direction along a surface of the first semiconductor layer. A semiconductor base layer of the second conductivity type is selectively formed on the surface of the second semiconductor pillar layer. A guard ring layer of the second conductivity type is formed surrounding the outermost periphery of the semiconductor base layer. The semiconductor base layer has a smaller junction depth than the guard ring layer.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is based on and claims the benefit of priority from prior Japanese Patent Application No. 2005-97164, filed on Mar. 30, 2005, the entire contents of which are incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a semiconductor device and a method for manufacturing the same. [0004] 2. Description of the Related Art [0005] The on-resistance of the vertical power MOSFET depends largely on the electrical resistance in the conduction layer (drift layer) portion. The electrical resistance of the drift layer depends on its impurity concentration. A higher impurity concentration can provide a lower on-resistance. A higher impurity concentration, however, will decrease the breakdown voltage of the PN junction between the drift layer and base layer. The impurity concentration thus cannot be higher than a limit determined by the breakdown voltage. A...

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Benefits of technology

[0008] A semiconductor device according to one aspect of the present invention comprises: a first semiconductor layer of a first conductivity type; a pillar layer formed on the first semiconductor layer, the pillar layer comprising a first semiconductor pillar layer of a first conductivity type and a second semiconductor pillar layer of a second conductivity type which are alternately formed in a first direction along a surface of the first semiconductor layer; a first main electrode electrically connected to the first semiconductor layer; a semiconductor base layer of the second conductivity type selectively formed on a surface of the second semiconductor pillar layer; a semiconductor diffusion layer of the first conductivity type selectively formed on a surface of the semiconductor base layer; a second main electrode formed in contact with the semiconductor base layer and semiconductor diffusion layer; and a control electrode formed via an insulating film on the semiconductor base layer, semiconductor diffusion layer, and first semiconductor pillar layer, the semiconductor device further comprising a guard ring layer of the second conductivity type formed surrounding an outermost periphery of the semiconductor base layer, and the semiconductor base layer having a smaller junction depth than the guard ring layer.

[0009] A method for manufacturing a semiconductor device according to one aspect of the present invention comprises: forming on a first semiconductor layer of a first conductivity type a second semiconductor layer having a lower impurity concentration than the first semiconductor layer; forming a plurality of equally spaced trenches

Problems solved by technology

This may cause electric field concentration in that region, which can cause destruction of the device.

In the conventional device structures, therefore, the MOS gate structure cannot have a small cell pitch which is comparable to the small cell of the super junction structure, thereby providing an insufficiently low on-resistance.

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