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Semiconductor package suitable for high voltage applications

a technology of semiconductors and semiconductor packages, applied in the direction of semiconductor devices, semiconductor/solid-state device details, electrical apparatus, etc., can solve the problem of limited maximum application voltage of semiconductor packages, and achieve the effect of increasing the creepage distance between outer leads and increasing the size of semiconductor packages

Inactive Publication Date: 2007-08-09
FAIRCHILD KOREA SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

"The present invention provides a semiconductor package suitable for high voltage applications, which increases the creepage distance between outer leads without increasing the size of the package. The semiconductor package includes a leadframe pad to which a semiconductor die is attached and inner leads electrically connected to the leadframe pad. The inner leads are covered by a molded housing, and outer leads extended from the inner leads protrude from the side surface of the molded housing to the outside. The outer leads have bent portions in portions where they are adjacent to the side surface of the molded housing, and at least one of the bent portions is covered by an extended portion of the molded housing. The semiconductor package also includes a depression on at least one of the surface of the molded housing between the first outer lead and the second outer lead, and a distance between the surface of the molded housing covering the portion of the first outer lead and the surface of the molded housing covering at least one of the bent portions of the second and third outer leads is 1 mm or more. The semiconductor package provides an increased safety margin for high voltage applications."

Problems solved by technology

If the creepage distance is insufficient, it is well-known in the art that the maximum application voltage of the semiconductor package is limited.

Method used

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  • Semiconductor package suitable for high voltage applications
  • Semiconductor package suitable for high voltage applications
  • Semiconductor package suitable for high voltage applications

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Embodiment Construction

[0032]FIG. 6 is a plane view of an embodiment of a semiconductor package according to the present invention. Referring to FIG. 6, the semiconductor package 100 according to the present invention has a structure in which three outer leads 121, 122 and 123 protrude out of a molded housing 110. Among those three outer leads 121, 122 and 123, a first outer lead 121 is disposed in a central portion of a side surface 112 of the molded housing 110. A second outer lead 122 and a third outer lead 123 are disposed on edge portions on the side surface 112 of the molded housing 110 to be respectively separated from the first outer lead 121 by a predetermined distance. Although it is not shown in FIG. 6, a semiconductor device such as metal-oxide-semiconductor field effect transistor (MOSFET) is buried in the molded housing 110, and respective electrodes of the semiconductor device are electrically connected to inner leads (not shown) which are extended from the outer leads 121, 122 and 123 via ...

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Abstract

A semiconductor package has a structure in which a leadframe pad to which a semiconductor die is attached and inner leads electrically connected to the leadframe pad are covered by a molded housing, and outer leads extending from the inner leads protrude from a side surface of the molded housing to the outside. The outer leads include a first outer lead disposed in a central portion of the molded housing, second and third outer leads respectively disposed in a right and left of the first outer lead. The second and third outer leads each have bent portions in portions where they are adjacent to the side surface of the molded housing, the bent portions protruding to increase a space between the first outer lead and the bent portions in the molded housing. At least one of the bent portions of the second and third outer leads is covered by an extended portion of the molded housing.

Description

[0001] This application is a continuation of U.S. application Ser. No. 10 / 762,075 filed Jan. 21, 2004, which claims the benefit of Korean Patent Application No. 2003-4025, filed on Jan. 21, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a semiconductor package, and more particularly, to a semiconductor package suitable for high voltage applications. [0004] 2. Description of the Related Art [0005] Generally, semiconductor devices such as diodes, thyristors, or MOS gate devices, for example, metal-oxide-semiconductor field effect transistors (MOSFET) and insulated gate bipolar transistors (IGBT), are formed in a silicon semiconductor die including a device junction. The die includes a metal drain electrode at its lower portion, a metal source electrode, and a gate electrode. The die is attached to a surface ...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L23/495H01L23/48H01L23/31
CPCH01L23/3107H01L23/49562H01L2924/13091H01L2924/1815H01L2924/0002H01L2924/00H01L23/48
Inventor SON, JOON-SEONAM, SHI-BAEKJEON, O-SEOB
Owner FAIRCHILD KOREA SEMICON
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