System and method for accommodating non-gaussian and non-linear sources of variation in statistical static timing analysis

Abstract

There is provided a system and method for statistical timing analysis and optimization of an electrical circuit having two or more digital elements. The system includes at least one parameter input and a statistical static timing analyzer and electrical circuit optimizer. The at least one parameter input is for receiving parameters of the electrical circuit. At least one of the parameters has at least one of a non-Gaussian probability distribution and a non-linear delay effect. The statistical static timing analyzer and electrical circuit optimizer is for calculating at least one of a signal arrival time and a signal required time for the electrical circuit using the at least one parameter and for modifying a component size of the electrical circuit to alter gate timing characteristics of the electrical circuit based upon the at least one of the signal arrival time and the signal required time.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation of co-pending U.S. patent Ser. No. 11 / 056,850, filed Feb. 11, 2005, which is incorporated by reference herein in its entirety.FIELD OF THE INVENTION [0002] The present invention generally relates to statistical static timing analysis and, more particularly, to a system and method for accommodating non-Gaussian and nonlinear sources of variation in statistical static timing analysis. BACKGROUND OF THE INVENTION [0003] It is commonly recognized that electrical characteristics of transistors and interconnects are not the same for different chips and even for the same chip at different time moments or chip locations. Variation of electrical characteristics can be due to variation of process parameters, changing of environmental conditions and even chips aging (Hot Carriers Injections, Negative Bias Temperature Instability, electromigration, and so forth). Variation of electrical characteristics results in ...

AI Technical Summary

Problems solved by technology

Unfortunately, with decreasing transistor size and interconnect width, the variation of electrical characteristics is getting proportionally larger.

Therefore, the approach to design for process corners, which used to work well, now results in too conservative and non-optimal designs because most design efforts and chip resources are spent to make chips function at very low-probability combinations of electrical characteristics.

Usually this requires enumeration of all signal propagation paths and integration in the space of parameters variations, which is an inefficient computational procedure.

In the statistical case, the situation is more complex because expressions, and not simply numbers, are operated upon.

Unfortunately, process parameters may have probability distributions, which are significantly different from Gaussian.

It is impossible to approximate certain asymmetric distributions by Gaussian ones with a reasonable error.

Another problem arises from the fact that some parameters can affect delay in a non-linear way.

Therefore, a linear approximation of delay dependence on variation is not always sufficiently accurate.

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