Boosting methods for NAND flash memory

Abstract

A floating gate memory array includes row control circuits that provide a programming voltage to a selected word line and provide a stair-like pattern of boosting voltages to unselected word lines. Boosting voltages descend with increased distance from the selected word line. Boosting voltages are increased in small increments up to their final values.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is related to U.S. patent application Ser. No. ______, entitled, “NAND Flash Memory with Boosting,” filed on the same day as the present application; which application is incorporated herein as if fully set forth in its entirety.BACKGROUND OF THE INVENTION [0002] This invention relates generally to non-volatile semiconductor memories of the flash EEPROM (Electrically Erasable and Programmable Read Only Memory) type, particularly to structures and methods of operating NAND types of memory cell arrays. All patents, patent applications and other material cited in the present application are hereby incorporated by reference in their entirety. [0003] There are many commercially successful non-volatile memory products being used today, particularly in the form of small form factor cards, which use an array of flash EEPROM cells. [0004] An example memory system is illustrated by the block diagram of FIG. 1. A memory cell array...

AI Technical Summary

Benefits of technology

The patent describes a boosting voltage scheme for a memory device that applies higher boosting voltages to certain word lines to improve programming efficiency. The boosting voltages are applied in a stair-like pattern, with higher voltages on the selected word line and nearby unselected word lines, and lower voltages on word lines farther away from the selected word line. This approach helps to reduce disturbances caused by the higher voltages and allows for a more uniform charging of the floating gates. Additionally, the patent describes a modified version of the boosting voltage scheme that combines the use of an isolating voltage to further confine the boosting to a specific region. The patent also describes a method for increasing the final voltage on the selected word line while maintaining the boosting voltage on the unselected word lines. Overall, the patent provides technical improvements for programming efficiency and reduced disturbances in memory devices.

Problems solved by technology

However, by only applying higher boosting voltage to a limited number of word lines, problems caused by such higher boosting voltage (boosting voltage disturb) are kept at a low level.

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