Boosting methods for NAND flash memory

a boosting method and flash memory technology, applied in static storage, digital storage, instruments, etc., can solve the problems of low level caused by such a high boosting voltage (boosting voltage disturbance) and achieve the effect of reducing programming voltage, high boosting voltage, and high boosting voltag

US20070258286A1Inactive Publication Date: 2007-11-08SANDISK TECH LLC
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Patent Information

Authority / Receiving Office
US · United States
Patent Type
Applications(United States)
Current Assignee / Owner
Publication Date
2007-11-08
Estimated Expiration
Not applicable · inactive patent

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Abstract

A floating gate memory array includes row control circuits that provide a programming voltage to a selected word line and provide a stair-like pattern of boosting voltages to unselected word lines. Boosting voltages descend with increased distance from the selected word line. Boosting voltages are increased in small increments up to their final values.
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Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is related to U.S. patent application Ser. No. ______, entitled, “NAND Flash Memory with Boosting,” filed on the same day as the present application; which application is incorporated herein as if fully set forth in its entirety.BACKGROUND OF THE INVENTION

[0002] This invention relates generally to non-volatile semiconductor memories of the flash EEPROM (Electrically Erasable and Programmable Read Only Memory) type, particularly to structures and methods of operating NAND types of memory cell arrays. All patents, patent applications and other material cited in the present application are hereby incorporated by reference in their entirety.

[0003] There are many commercially successful non-volatile memory products being used today, particularly in the form of small form factor cards, which use an array of flash EEPROM cells.

[0004] An example memory system is illustrated by the block diagram of FIG. 1. A memory cell array...

Examples

Embodiment Construction

[0047]FIG. 5 shows a cross section of a portion of a NAND string in a flash memory array undergoing programming according to an embodiment of the present invention. FIG. 5 shows capacitors representing capacitive coupling between some of the elements of the NAND string. Not all couplings between elements are shown. For example, word lines are strongly coupled to directly underlying floating gates allowing floating gates to be programmed. Also, both floating gates and word lines are coupled to a portion of the underlying substrate. The particular couplings shown are chosen to illustrate some of the advantages of this embodiment over prior art programming schemes. Also, the couplings shown are becoming more significant as lateral dimensions of NAND arrays are scaled down in size more rapidly than vertical dimensions are scaled.

[0048]FIG. 6 shows voltages applied to word lines WLn−3 to WLn+3 of FIG. 5 according to one embodiment of the present invention. WLn is the selected word line ...