Wafer-level stack package

Inactive Publication Date: 2009-07-02
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0011]Example embodiments provide a wafer-level stack package capable of reducing the inductance of a w

Problems solved by technology

Thus, supply characteristics of a pow

Method used

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  • Wafer-level stack package
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Examples

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Embodiment Construction

[0038]Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown. The present general inventive concept may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

[0039]It will be understood that when an element or layer is referred to as being “on,”“connected to” or “coupled to” another element or layer, it can be directly on connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,”“directly connected to” or “directly co...

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PUM

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Abstract

A wafer-level stack package includes semiconductor chips, first connection members, a second connection member, a substrate and an external connection terminal. The semiconductor chips have a power/ground pad and a signal pad. The first connection members are electrically connected to the power/ground pad and the signal pad of each of the semiconductor chips. The second connection member is electrically connected to at least one of the power/ground pads of each of the semiconductor chips, the power/ground pads being connected to the first connection members. The substrate supports the stacked semiconductor chips, the substrate including wirings that are electrically connected to the first connection members and the second connection member. The external connection terminal is provided on a surface of the substrate opposite to a surface where the semiconductor chips are stacked, wherein the external connection terminals are electrically connected to the wirings, respectively.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 2007-138431, filed on Dec. 27, 2008 in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety.BACKGROUND[0002]1. Field of the Invention[0003]Example embodiments relate to a wafer-level stack package and a method of manufacturing a wafer-level stack package. More particularly, example embodiments relate to a wafer-level stack package including semiconductor chips processed at the wafer level and a method of manufacturing the wafer-level stack package.[0004]2. Description of the Related Art[0005]Semiconductor packages are becoming miniaturized and lightweight according to the miniaturization trend of electronic products using semiconductor devices. Examples of the miniaturized and lightweight semiconductor package may include a stack package. In the stack package, stacked semiconductor ...

Claims

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Application Information

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IPC IPC(8): H01L23/48
CPCH01L21/76898H01L25/0657H01L25/50H01L2225/06513H01L2224/16H01L2225/06541H01L2225/06551H01L2924/15311H01L2225/06527H01L2224/05009H01L2224/05548H01L2224/05001H01L2924/00014H01L2224/16145H01L2224/02379H01L2224/92144H01L2224/05599H01L2224/05099H01L23/12
Inventor KANG, SUN-WONBAEK, SEUNG-DUK
Owner SAMSUNG ELECTRONICS CO LTD
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