Semiconductor memory device, memory module including the same, and data processing system

Abstract

To provide a semiconductor device including a skew detecting circuit activated in a write leveling mode, and an ODT control circuit that activates a terminating resistance circuit connected to a data strobe terminal by using an ODT signal. The ODT control circuit includes counters that delay the ODT signal, activates the terminating resistance circuit by using the ODT signal having passed the counters in a normal operation mode, and activates the terminating resistance circuit by using the ODT signal having bypassed the counters in the write leveling mode. With this configuration, in the write leveling mode, a write leveling operation can be performed quickly without waiting for latency of the ODT signal.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device having a write leveling mode for measuring a skew between a clock signal and a data strobe signal. The present invention also relates to a module including this semiconductor device and to a data processing system.[0003]2. Description of Related Art[0004]Transmission and reception of read data and write data between a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) and a memory controller may be performed synchronously with a data strobe signal. For example, in a write operation, a memory controller supplies a data strobe signal and write data to a semiconductor memory device, and the semiconductor memory device fetches the write data synchronously with the data strobe signal.[0005]However, the write data fetched by the semiconductor memory device is transferred to a memory cell arra...

AI Technical Summary

Benefits of technology

[0016]According to the semiconductor device of the present invention, when the device enters the write leveling mode, a counter that counts latency of the ODT signal is bypassed. Therefore, when the ODT signal is input, the terminating resistance circuit can be immediately activated asynchronously with a clock. Accordingly, the semiconductor device can quickly perform a write leveling operation without waiting for the latency of the ODT signal. Furthermore, because the terminating resistance circuit is not activated constantly but is activated based on the ODT signal, power consumption does not increase.

[0017]According to the module of the present invention, even when clock terminals provided in semiconductor devices are flyby-connected, a skew generated by this configuration can be quickly adjusted.

[0018]According to the data processing system of the present invention, even when the device periodically or cyclically enters a write leveling mode during an operation after starting a system, a reduction of processing capacity due to this entry can be minimized.

Problems solved by technology

However, the write data fetched by the semiconductor memory device is transferred to a memory cell array synchronously with a clock signal, which is different from the data strobe signal.

Therefore, when a skew exists between the data strobe signal and the clock signal, a write operation cannot be performed correctly.

Consequently, the write leveling operation takes time disadvantageously.

While this problem is not so critical when a system is started or a module is reset, it becomes critical when write leveling is periodically performed in an operation after the system is started, because it leads to drop of system performance.

However, this method leads to increase of power consumption.

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