Common mode tracking receiver

Abstract

A clock receiver (301) on an integrated circuit (202) includes a programmable AC voltage divider (502) for receiving, through an input capacitor (406), a clock signal (206) from a clock generator (204) off the integrated circuit and for outputting a modified signal that has a reduced voltage swing, an inverter (440) coupled to the programmable voltage divider, and a common mode setting circuit (506), coupled to an input and an output of the inverter. The common mode setting circuit sets and maintains a common mode at the input of the inverter in response to a voltage at the input of the inverter and a voltage at the output of the inverter. The strength of transistors in the common mode tracking circuit tracks the strength of transistors in the inverter such that the common mode at the input to the inverter tracks a trip point of the inverter.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]This invention relates generally to clock receivers, and more specifically to an AC-coupled clock receiver for receiving a single-ended clock signal.[0003]2. Related Art[0004]FIG. 1 is a schematic diagram of a prior art clock receiver 101. An external reference clock generator provides a clock signal to an external clock input node 102. There is a capacitor 106 between the external clock input node 102 and a first node 103 of the clock receiver 101 for coupling alternating current (“AC”) of the clock signal to the first node 103. The clock signal is a single-ended clock signal and may be one of several voltages higher than the operating voltage of the clock receiver 101. A phase-locked loop control logic supplies a 3-bit receiver select signal 107 to a receiver select input node 104. The clock receiver 101 comprises a first programmable transistor 111, a second programmable transistor 112, and a third programmable trans...

AI Technical Summary

Problems solved by technology

If the clock receiver 101 is receiving the clock signal from a higher voltage domain than that of the clock receiver 101, and if the clock receiver has not finished powering-up, the clock receiver can be damaged.

Within a voltage domain, a voltage swing variation of the clock signal and / or a variation of the trip point of the inverter 140 can distort the duty cycle of the received clock signal, and may permanently damage of the clock receiver 101.

However, these other known prior art receivers do not fully compensate for voltage swing variations within a voltage domain.

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