Chip package and fabrication method thereof

Abstract

A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001]This application claims the benefit of U.S. Provisional Application No. 61 / 265,708, filed on Dec. 1, 2009, the entirety of which is incorporated by reference herein.BACKGROUND OF THE INVENTION [0002]1. Field of the Invention[0003]The present invention relates to a chip package, and in particular relates to a chip package which can protect conductive pads from damage during a cutting process and a redistribution stack layer and a fabrication method thereof.[0004]2. Description of the Related Art[0005]Wafer level packaging technology has been developed for packaging chips. After a wafer level package is completed, a cutting process is performed between chips to separate the chips from each other.[0006]However, when using a cutter to form an opening between the chips in the cutting process, a lot of chipping is produced. The chippings damage and scratch bonding pads of the chip during the cutting process, such that the reliability of wire b...

AI Technical Summary

Benefits of technology

The patent describes a chip package and a method for making it. The chip package has a semiconductor substrate with a chip and conductive pads at the edges. A layer of insulating protective material is placed over the chip and conductive pads, and a packaging layer is placed on top of the insulating protective material. The packaging layer is patterned to expose the insulating protective material at the edges, and the insulating protective material is removed to expose the conductive pads. This makes it easier to connect the chip to external components.

Problems solved by technology

However, when using a cutter to form an opening between the chips in the cutting process, a lot of chipping is produced.

The chippings damage and scratch bonding pads of the chip during the cutting process, such that the reliability of wire bonding of the chip package is reduced following subsequent processes and the electrical property of the conventional chip package is poor.

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