Airgap-containing interconnect structure with patternable low-k material and method of fabricating

a low-k material and air gap technology, applied in the direction of electrical equipment, semiconductor devices, semiconductor/solid-state device details, etc., can solve the problems of reducing the number of layers, the organic anti-reflective coating is typically not suitable for lithography, and the organic anti-reflective coating cannot withstand high-temperature processes, so as to reduce the complexity of the fabrication of current interconnect structures, reduce the time and cost of fabrication, and reduce the number of layers

Inactive Publication Date: 2012-09-13
GLOBALFOUNDRIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach simplifies the fabrication of interconnect structures, reduces manufacturing costs and time, and enhances the reliability of low-k dielectric materials by avoiding the complexities of sacrificial layers and plasma etching, while maintaining pattern integrity and reducing the dielectric constant.

Problems solved by technology

Unfortunately, conventional organic antireflective coatings are generally not suitable for the lithography of a patternable low-k material as the antireflective coating layer is a permanent part of the interconnect structure.
These organic antireflective coatings typically cannot withstand high temperature processes such as, for example, the high temperature during either the curing of the patternable low-k dielectric or annealing of the interconnect metal.

Method used

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  • Airgap-containing interconnect structure with patternable low-k material and method of fabricating
  • Airgap-containing interconnect structure with patternable low-k material and method of fabricating
  • Airgap-containing interconnect structure with patternable low-k material and method of fabricating

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second embodiment

[0099]In a second embodiment, a Si:C:O:H film is deposited under the following conditions: precursor=tetramethylsilane at a flow of 10 sccm mixed with oxygen at a flow of 2 sccm, pressure in reactor=200 mtorr, substrate temperature=180° C., substrate bias=−200 V.

third embodiment

[0100]In a third embodiment, a Si:C:H film is deposited under the following conditions: precursor=trimethylsilane at a flow of 10 sccm, pressure in reactor=200 mtorr, substrate temperature=60° C., substrate bias=−200 V.

fourth embodiment

[0101]In a fourth embodiment, a Si:C:O:H film is deposited under the following conditions: precursor=trimethylsilane at a flow of 10 sccm mixed with oxygen at a flow of 2 sccm, pressure in reactor=200 mtorr, substrate temperature=60° C., substrate bias=−200 V.

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Abstract

The present invention provides a method of fabricating an airgap-containing interconnect structure in which a patternable low-k material replaces the need for utilizing a separate photoresist and a dielectric material. Specifically, this invention relates to a simplified method of fabricating single-damascene and dual-damascene airgap-containing low-k interconnect structures with at least one patternable low-k dielectric and at least one inorganic antireflective coating.

Description

CROSS REFERENCE TO RELATED APPLICATION[0001]This application is a divisional of U.S. patent application Ser. No. 11 / 971,470, filed Jan. 9, 2008 the entire content and disclosure of which is incorporated herein by reference.FIELD OF THE INVENTION[0002]The present invention relates to an interconnect structure and a method of fabricating the same. More specifically, the present invention relates to an interconnect structure including a patternable dielectric material as an interconnect dielectric and at least one airgap within the patternable dielectric material. The present invention also provides a method of fabricating such a patternable dielectric interconnect structure.BACKGROUND OF THE INVENTION[0003]It is widely known that the speed of propagation of interconnect signals is one of the most important factors controlling overall circuit speed as feature sizes are reduced and the number of devices per unit area as well as the number of interconnect levels are increased. Throughout...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): H01L23/532
CPCH01L21/76808H01L21/7682H01L21/76835H01L23/5222H01L23/5329H01L23/53295H01L2924/12044H01L2924/0002H01L2924/00H01L23/532
InventorLIN, QINGHUANG
OwnerGLOBALFOUNDRIES INC