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State retention power gated cell

a gated cell and state retention technology, applied in the field of integrated circuits, can solve the problems of high routing congestion and low utilization rate of sea gates, high well-leakage, and need for an increase in die siz

Active Publication Date: 2015-04-02
NXP USA INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention provides an integrated circuit with a logic cell that includes a state retention power gated cell (SRPG cell) that can retain necessary information even in a standby or sleep mode. The invention solves the problem of low power consumption and high routing congestion in conventional SRPG cells. The invention also includes a multi-row height layout that allows for efficient power routing and utilization of the semiconductor device. The technical effects of the invention include improved efficiency and reduced leakage in the standby or sleep mode.

Problems solved by technology

In current SRPG cells, the second power supply VDDC consumes a lot of routing resources, which results in high routing congestion and low utilization in Sea of Gates (SOG).
The low utilization of the SOG can cause a need for an increased die size.
Further, some of the circuitry, for example, MOS transistors, of the SRPG cell is continuously powered in the standby mode, resulting in relatively high well-leakage.

Method used

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Embodiment Construction

[0017]Hereinafter, the embodiments of the present invention will be described in conjunction with the accompanying drawings.

[0018]As used herein, the term “semiconductor device” (may be simplified as “device”) refers to any devices that can operate by partially or fully using semiconductor characteristics, such as a MOS transistor. As used herein, the term “coupling” and its variations are not intended to be limited to directly coupling or mechanical coupling.

[0019]The present invention provides an SRPG cell that is laid out into a multi-row height (×2 height for instance or ×N). The multi-row height layout allows for efficient power routing such that it saves on metal routing resources. Saving routing resources allows a more efficient and full SOG utilization for an SOC using the SRPG cell. The SPRG cell also has fewer N-wells tied to VDDC and less N-well leakage.

[0020]In one embodiment of the present invention, a logic cell arranged in two or more rows includes an active layer hav...

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PUM

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Abstract

A state retention power gated cell includes a logic cell arranged in two or more rows. The logic cell has an active layer including at least a first well and a second well disposed in first and second rows, respectively. In a normal operation mode, the first well is powered with a first bias voltage, the second well is powered with a second bias voltage, the first power supply line is powered with VDDC, and the second power supply line is powered with VDD. In a standby mode, the first well preferably is powered down, the second well is powered with the second bias voltage, the first power supply line is powered with VDDC, and the second power supply line is powered down.

Description

BACKGROUND OF THE INVENTION[0001]The present invention relates to an integrated circuit including a logic cell and, more particularly, to a state retention power gated cell.[0002]In current integrated circuits (IC), low power consumption is an important concern, particularly for mobile devices where power storage is limited. In this regard, a number of electronic devices have a normal operation mode in which the ICs in the device are powered so that they can operate normally, for example, at high speed (frequency), and a standby (or sleep) state in which a part of (or, even most of) the ICs are powered down. However, even in the power down or sleep state, the operation state (associated information) of some of the circuits must be retained.[0003]One way to retain state is to use a logic cell, for example, a State Retention Power Gated (SRPG) cell, to retain necessary information when in the standby or sleep mode. An SRPG cell has two power supplies. A primary power supply (VDD) is u...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H03K3/012H03K3/356H03K19/00
CPCH03K3/012H03K3/356H03K19/0008H01L27/0207G06F30/00H01L27/0233
Inventor TAN, MIAOLINCHENG, ZHIHONGFU, JUANWANG, PEIDONGWANG, YALI
Owner NXP USA INC