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Semiconductor device for restraining creep-age phenomenon and fabricating method thereof

a technology of creep-age phenomenon and semiconductor device, which is applied in the direction of semiconductor device, semiconductor/solid-state device details, electrical apparatus, etc., can solve the problems of increased creep-age phenomenon, limited method of changing creep-age distance, and potential safety hazards

Active Publication Date: 2015-06-18
ALPHA & OMEGA SEMICON INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This design effectively increases the creepage distance by up to 4 mm, improving electrical safety and compliance with safety standards, while maintaining a compact device size and preventing creepage phenomenon under harsh environmental conditions.

Problems solved by technology

In addition, with the development of main stream technology, the device size often needs to be minimized, which causes the insulating materials surrounding the leads being extremely closer to each other and subjected to electric polarization, so that the insulating materials are electrified to affect the normal operation of the device, or to cause the potential safety hazards; particularly, a creep-age phenomenon is increased under humidity or dust environments.
However, in the conventional devices described above, the method of changing the creep-age distance is very limited; especially it cannot restrain the creep-age phenomenon under the harsh environment when a high voltage is applied on the drain lead or source lead.

Method used

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  • Semiconductor device for restraining creep-age phenomenon and fabricating method thereof
  • Semiconductor device for restraining creep-age phenomenon and fabricating method thereof
  • Semiconductor device for restraining creep-age phenomenon and fabricating method thereof

Examples

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Embodiment Construction

[0017]A part of a metal lead frame 100 is shown in FIG. 2, which is a standard TO single-row straight plugging package lead frame generally including a plurality of chip mounting units 110, one of which is shown in FIG. 3A. Each chip mounting unit 110 at least includes a square die paddle 111 for attaching a semiconductor chip. A plurality of leads 113,114 and 115 arranged side by side closed to an edge 111a of the die paddle 111, wherein the leads 113 and 114 are separated from the die paddle 111, while the lead 115 is connected with the die paddle 111, and the lead 114 is arranged in between and adjacent to the leads 113 and 115. A fork-shaped heat sink 112 having a notch is connected with the die paddle 111 at the opposite edge relative to the edge 111a. The inner side of the notch is in arc shape or close to a semicircle, which can be used for positioning the lead frame 100. It should be noted that the heat sink 112 described hereby is only one of a plurality selection modes, so...

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Abstract

The present invention relates generally to a semiconductor device and, more specifically, to optimizing the creep-age distance of the power semiconductor device and a preparation method thereof. The power semiconductor device includes a chip mounting unit with a die paddle and a plurality of leads arraged side by side located close to one side edge of the die paddle in a non-equidistant manner, a semiconductor chip attached on the die paddle, and a plastic packaging body covering the die paddle, the semiconductor chip, where the plastic packing body includes a plastic extension portion covering at least a part of a lead shoulder of a lead to obtain better electrical safety distance between the terminals of the semiconductor device, thus voltage creep-age distance of the device is increased.

Description

FIELD OF PRESENT INVENTION[0001]The present invention generally relates to a semiconductor device, in particular, the present invention aims at providing a power semiconductor device for optimizing an electric clearance and increasing a voltage creep-age distance and a fabricating method thereof, in order to obtain a better electric safety distance between different terminals of the semiconductor device.BACKGROUND OF RELATED ART[0002]In a traditional power semiconductor device, a large current is generally flowed or a high voltage is applied through the leads of the device. In addition, with the development of main stream technology, the device size often needs to be minimized, which causes the insulating materials surrounding the leads being extremely closer to each other and subjected to electric polarization, so that the insulating materials are electrified to affect the normal operation of the device, or to cause the potential safety hazards; particularly, a creep-age phenomenon...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L23/495
CPCH01L23/49503H01L23/49534H01L23/49575H01L23/3107H01L23/3121H01L23/49562H01L21/561H01L24/06H01L24/29H01L24/32H01L24/40H01L24/48H01L24/49H01L24/73H01L24/97H01L2224/04034H01L2224/04042H01L2224/06051H01L2224/06181H01L2224/291H01L2224/2929H01L2224/29339H01L2224/32245H01L2224/48247H01L2224/49111H01L2224/49175H01L2224/73263H01L2224/73265H01L2224/97H01L2924/13055H01L2924/13091H01L2924/1815H01L2224/40247H01L2924/181H01L2224/0603H01L2924/00014H01L2224/371H01L2224/84801H01L24/37H01L2224/8485H01L2224/85H01L2224/83H01L2924/00012H01L2224/84H01L2924/014H01L2924/00H01L2224/45099H01L2224/45015H01L2924/207H01L2224/73221
Inventor NIU, ZHI QIANGYILMAZ, HAMZALU, JUNWANG, FEI
Owner ALPHA & OMEGA SEMICON INC