Making electrical components in handle wafers of integrated circuit packages

Abstract

A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region. The capacitor has a pair of electrodes, each coupled to one of a pair of conductive pads, at least one of which is disposed on a lower surface of the handle wafer. An interposer having an upper surface with a conductive pad and at least one semiconductor die disposed thereon is also provided. The die has an integrated circuit that is electroconductively coupled to a redistribution layer (RDL) of the interposer. The lower surface of the handle wafer is bonded to the upper surface of the interposer such that the die is disposed below or within the cavity and the electroconductive pad of the handle wafer is bonded to the electroconductive pad of the interposer in a metal-to-metal bond.

Description

BACKGROUND[0001]1. Technical Field:[0002]This disclosure generally relates to making integrated circuit packages with “handle wafers,” and more particularly, to making discrete electrical components, such as capacitors, within the handle wafers of such packages.[0003]2. Related Art:[0004]The “wafer level” or “wafer scale” production of integrated circuit (IC) packages has proliferated in recent years, due primarily to the economies of scale that such production techniques afford, together with the concomitant reduction in size and cost of the resulting packages. Examples of such IC packages and methods for making them can be found in, e.g., commonly owned U.S. patent application Ser. No. 14 / 214,365 by H. Shen, et al., filed Mar. 14, 2014, and entitled “Integrated Circuits Protected by Substrates with Cavities, and Methods of Manufacture,” the entire disclosure of which is incorporated herein by reference.[0005]In one of only many possible embodiments of such packages, the packages, ...

AI Technical Summary

Benefits of technology

This approach enables the maximization of capacitor size and capacitance, reducing the size of semiconductor packages while providing enhanced functionality by utilizing otherwise 'wasted' volume in the handle wafer.

Problems solved by technology

However, a practical problem arises when the interposer wafer of such packages is made substantially thin, in that this limits the vertical height of the discrete electrical components, such as capacitors, that can be built into the thickness of the interposer, and hence, their maximum surface area or capacitance.

Accordingly, a long felt but as yet unsatisfied need exists for methods and apparatus that overcome the foregoing and other problems of the prior art.

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