Multi-level memory apparatus and data sensing method thereof

a multi-level memory and data sensing technology, applied in the field of memory devices including multi-level memory cells, can solve the problems of volatile memory of dram and the limitation of data processing speed in the structur

Active Publication Date: 2016-04-28
SK HYNIX INC +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This solution reduces power consumption and enhances data processing speed by allowing non-continuous cell current flow during data detection, enabling simultaneous MSB and LSB determination operations.

Problems solved by technology

However, the DRAM is a volatile memory due to a leakage current of the capacitor.
Furthermore, since the current is continuously supplied to the memory cell 102 until the data stored in the memory cell 102 is confirmed, which may prevent some other operations from being simultaneously performed, such a structure has a limitation in improving a data processing speed.

Method used

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  • Multi-level memory apparatus and data sensing method thereof
  • Multi-level memory apparatus and data sensing method thereof
  • Multi-level memory apparatus and data sensing method thereof

Examples

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Embodiment Construction

[0029]Various embodiments will be described below in more detail with reference to the accompanying drawings. Embodiments may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present disclosure.

[0030]FIG. 2 illustrates a part of a multi-level memory device in accordance with an embodiment. FIG. 3 illustrates an operation of the multi-level memory device shown in FIG. 2 in accordance with an embodiment.

[0031]The multi-level memory device may include a memory cell 210, a detection current generation circuit 220, a most significant bit (MSB) determination circuit 230, a current / voltage conversion circuit 240, a chargin...

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Abstract

A multi-level memory device may include a most significant bit (MSB) determination circuit configured to determine a plurality of MSBs by comparing a cell current flowing through a memory cell with a predetermined reference current, a current / voltage conversion circuit configured to convert a copied cell current obtained by copying the cell current into a cell voltage, a charging time determination circuit configured to determine a charging time during which the copied cell current is converted into the cell voltage and output a charging end signal, and a least significant bit (LSB) determination circuit configured to determine a plurality of LSBs according to the cell voltage and the charging end signal.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]The present application claims priority of Korean Patent Application No. 10-2014-0144746, filed on Oct. 24, 2014, which is incorporated herein by reference in its entirety.BACKGROUND[0002]1. Field[0003]Embodiments of the present disclosure relate to a semiconductor device, and more particularly, to a memory device including multi-level memory cells.[0004]2. Description of the Related Art[0005]A conventional DRAM includes a memory cell having a capacitor, and stores data while charging or discharging the memory cell. However, the DRAM is a volatile memory due to a leakage current of the capacitor. In order to address the above issue of the DRAM, nonvolatile memories have been developed. In particular, a phase change memory device including phase change memory cells have been developed.[0006]FIG. 1 schematically illustrates the configuration of a conventional phase change memory device shown in FIG. 4 of US Patent Laid-open Publication No. 2...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): G11C13/00
CPCG11C13/0004G11C13/004G11C11/56G11C11/5678G11C13/0002G11C13/0061G11C2013/0054
InventorRYU, SEUNG TAKKWON, JI WOOKJIN, DONG HWAN
OwnerSK HYNIX INC