Semiconductor devices

Abstract

A semiconductor device includes a phase comparison circuit, an output enablement signal generation circuit, and a data input / output (I / O) circuit. The phase comparison circuit compares a phase of a clock signal with a phase of a delay locked loop (DLL) clock signal to generate a phase information signal. The output enablement signal generation circuit latches an internal command in response to a first pre-control signal and outputs the latched internal command as an output enablement signal in response to an operation clock signal and a second pre-control signal. The output enablement signal generation circuit generates the first pre-control signal according to an internal clock signal and an input clock signal. The data I / O circuit receives input data and output the received input data as output data synchronized with a strobe signal in response to the output enablement signal.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]The present application claims priority under 35 U.S.C. 119(a) to Korean Patent Application No. 10-2016-0175758, filed on Dec. 21, 2016, which is incorporated herein by reference in its entirety.BACKGROUND1. Technical Field[0002]Embodiments of the present disclosure relate to semiconductor devices controlling input / output of signals of a pipe latch circuit using a signal generated by a replica delay circuit.2. Related Art[0003]Fast semiconductor devices are increasingly desirable with the improvement of their integration density. Double data rate (DDR) synchronous dynamic random access memory (DRAM) devices operating in synchronization with rising edges and falling edges of a clock signal have increased the operation speed thereof. Data strobe signals may be used in the DDR synchronous DRAM devices to minimize timing margin loss, which results from a timing skew between DDR synchronous DRAM devices, a variation of an access time according ...

AI Technical Summary

Benefits of technology

This patent is about a semiconductor device that includes a circuit to compare two signals and generate an output enablement signal based on those signals. The device also includes a circuit to generate pre-control signals and an input / output control signal to synchronize data input and output. The technical effects of this patent are improved accuracy and reliability in the synchronization of data input and output in a semiconductor device.

Problems solved by technology

In addition, the pre-control signal generation circuit delays the internal clock signal using a first delay circuit to generate an operation clock signal.

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