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Stacked semiconductor device

a semiconductor device and multi-channel technology, applied in semiconductor/solid-state device testing/measurement, semiconductor/solid-state device details, instruments, etc., can solve problems such as tsv cracking, bump contact failure, and various types of defects

Active Publication Date: 2018-08-30
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent covers a stacked semiconductor device with a multi-channel structure that can verify if through-electrodes are operating normally based on channel information. The device includes a base die and a plurality of core dies stacked over the base die which can communicate with allocated channels through a plurality of through-electrodes. Each core die has a through-electrode scan unit and a defect detection unit which can detect whether the through-electrodes have a defect by performing a down scan and an up scan. The technical effect of this patent is to enhance the reliability and quality of the stacked semiconductor device by ensuring the proper operation of through-electrodes.

Problems solved by technology

In the TSVs, various types of defects may occur.
The defects may include a void which occurs when a TSV is not completely filled with a conductive material, a bump contact fail which occurs when a chip is bent or a bump material is moved, and a crack of a TSV.

Method used

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Embodiment Construction

[0020]Various embodiments will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention. It is also noted that in this specification, “connected / coupled” refers to one component not only directly coupling another component but also indirectly coupling another component through an intermediate component. In addition, a singular form may include a plural form as long as it is not specifically mentioned in a sentence.

[0021]Hereafter, a semiconductor memory system will be described as an example of a stacked...

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Abstract

A stacked semiconductor device may include: a base die; and a plurality of core dies stacked over the base die, and suitable for communicating with allocated channels through a plurality of through-electrodes. Each of the core dies may include: a through-electrode scan unit enabled according to allocated channel information, and suitable for performing a down scan of transmitting a signal downward through through-electrodes connected in a column direction among the through-electrodes and an up scan of transmitting a signal upward through the through-electrodes connected in the column direction; and a defect detection unit suitable for detecting whether the through-electrodes have a defect, based on the down scan and the up scan.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]The present application claims priority of Korean Patent Application No. 10-2017-0026018, filed on Feb. 28, 2017, which is herein incorporated by reference in its entirety.BACKGROUND1. Field[0002]Various embodiments relate to a semiconductor design technology, and more particularly, to a stacked semiconductor device with a multi-channel structure.2. Description of the Related Art[0003]With the rapid development of semiconductor technology, the packaging technology for semiconductor integrated devices has required high integration and high performance. Therefore, a variety of techniques for a three-dimensional (3D) structure in which a plurality of semiconductor chips are vertically stacked have been developed, in addition to a two-dimensional (2D) structure in which semiconductor chips having integrated circuits formed therein are two-dimensionally arranged on a printed circuit board (PCB) through wires or bumps.[0004]Such a 3D structure ...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L21/66H01L25/065G01R31/28
CPCH01L22/32H01L25/0652G01R31/2884H01L2225/06541G01R31/024G11C5/063G01R31/318513G11C29/025G11C29/26G11C29/32G11C29/44H01L2224/16145H01L2224/16225H01L2924/15192H01L2924/15311G11C29/12H01L25/073H01L23/481H01L25/18H01L23/58H01L25/0657G01R31/275H01L25/50G11C5/06
Inventor KIM, JI-HWANLEE, DONG-UK
Owner SK HYNIX INC