Pipelined latches to prevent metastability

Abstract

Memory devices may receive data from data processing devices for storage and processing during write operations. The received data may be accompanied by a data strobing signal that informs the memory device that data available in the bus is ready for latching. The data strobing signal may be provided via a tri-stateable or bidirectional connection and, as a result, during initialization of a write operation, the input circuitry may suffer from metastability during an initial transient period. The present application discusses methods and systems that may mitigate metastability by preventing invalid states in the input circuitry when data strobing signal is invalid or disabled. Certain embodiments determine if the data strobing signal is a valid input and, accordingly, adjust the received signal to a fixed value or to a previously received value. The use of latches and differential amplifiers to perform these functions is also discussed.

Description

BACKGROUND1. Field Of The Invention[0001]The present disclosure relates to memory devices, and more specifically to methods to mitigate metastability effects in clocking signals during data access in memory devices.2. Description Of The Related Art[0002]Random access memory (RAM) devices, such as the ones that may be employed in electrical devices to provide data processing and / or storage, may provide direct availability to addressable data storage cells that form the memory circuitry of the device. Certain RAM devices, such as dynamic RAM (DRAM) devices may, for example, have multiple memory banks having many addressable memory elements. RAM devices may also have a command interface that may receive addresses and instructions (e.g., read, write, etc.) for operations that may be associated with those addresses and decoding circuitry that may process the instructions and the addresses to access the corresponding memory banks.[0003]Commands and data to access to the addressable memory...

AI Technical Summary

Benefits of technology

This approach reduces the lag in receiving and storing data after a write command by minimizing the recovery time from metastability, ensuring accurate data processing and reducing the risk of incorrect initialization.

Problems solved by technology

The disabled clock signal may cause uncertainty in the state of logic circuitry that processes data strobing and / or data inputs in the memory device, which may lead to metastability.

The metastability may cause delays and / or lags when communication between processing circuitry and the memory device is reestablished and the clocking signal is resumed.

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