PLL with Beat-Frequency Operation

Abstract

A PLL has a controlled oscillator with a limited frequency range. It has a phase accumulator and a phase predictor whose ranges are limited to a value K related to their bit width. K is less than the ratio of the maximum output frequency and the minimum reference frequency. The PLL locks the output frequency to a value higher than the FCW times the reference frequency. The PLL includes a means for setting the output frequency to a target frequency before achieving final lock. The PLL may have a lock detector. After acquiring lock, the PLL may reduce the bit width and K value, for example by cutting power to or switching off some of the bits, or by switching off slow counters in a multi-counter system.

Description

CROSS REFERENCES TO OTHER APPLICATIONS[0001]This application claims priority from U.S. Provisional Patent Application Ser. No. 62 / 671,822, entitled Digital Circuits and Methods for Phase-Locked Loops, filed on May 15, 2018, which is hereby incorporated by reference as if set forth in full in this application for all purposes.[0002]This application is related to the following application, U.S. patent application Ser. No. <serial no>, entitled Phase Accumulator with Improved Accuracy, filed concurrently herewith, which is hereby incorporated by reference, as if set forth in full in this specification.[0003]This application is related to the following application, U.S. patent application Ser. No. <serial no>, entitled Power-Saving Phase Accumulator, filed concurrently herewith, which is hereby incorporated by reference, as if set forth in full in this specification.[0004]This application is related to the following application, U.S. patent application Ser. No. <serial no...

AI Technical Summary

Benefits of technology

The invention provides a method for locking the output clock's frequency to the reference clock's frequency using multiple frequency lock ranges. This reduces the uncertainty and certainty of locking to the desired output frequency, while also reducing the power consumption of the circuit. Additionally, the invention provides a second beat-frequency PLL that uses a modulo-K counter and a phase predictor to switch between different frequency lock ranges and predict the phase of the output clock. This allows for more efficient and accurate locking of the output clock's frequency.

Problems solved by technology

Compared to a PLL, an FLL lacks the integration or accumulation over time.

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