Non-volatile memory

Abstract

A non-volatile memory having memory cells is provided. The memory cell includes a source region and a drain region, a select gate, a dummy select gate, a floating gate, an erase gate, and a control gate. The select gate is disposed on the substrate between the source region and the drain region. The floating gate is disposed on the substrate between the select gate and the source region, and a top portion of the floating gate has corners in symmetry. The height of the floating gate is lower than the height of the select gate. The erase gate is provided on the source region and covers the corner at the side of the source. The control gate is disposed on the erase gate and the floating gate.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application claims the priority benefit of Taiwan application serial no. 107139903, filed on Nov. 9, 2018. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.BACKGROUND OF THE INVENTIONField of the Invention[0002]The invention relates to a semiconductor device and a manufacturing method thereof. More particularly, the invention relates to a non-volatile memory and a manufacturing method thereof.Description of Related Art[0003]A non-volatile memory allows multiple data writing, reading and erasing operations, and the stored data is retained even after power is cut off. With these characteristics, non-volatile memories have been widely used in personal computers and electronic equipment.[0004]The typical design of a non-volatile memory includes a stack-gate structure, and the stack-gate structure includes a tunneling oxide layer, a floating gate, an int...

AI Technical Summary

Benefits of technology

[0008]The invention provides a non-volatile memory and a manufacturing method thereof capable of being operated at a low operational voltage, so as to facilitate the reliability of the semiconductor device.

[0009]The invention provides a non-volatile memory and a manufacturing method thereof capable of reducing the gate resistance, so as to facilitate the operational speed of the semiconductor device.

[0010]The invention provides a non-volatile memory and a manufacturing method thereof capable of increasing the level of integration of the device.

Problems solved by technology

Thus, an abnormal punch through between the drain and the source may occur easily, which greatly affects the electrical performance of the memory cell.

In addition, the electrons repetitively passing through the tunneling oxide layer during programming or erasing of memory cells may wear off the tunneling oxide layer and thus reduce the reliability of the memory device.

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