Method for improving interlevel dielectric gap filling over semiconductor structures having high aspect ratios

Abstract

A novel sequence of process steps is provided for forming void-free interlevel dielectric layers between closely spaced gate electrodes. Closely spaced gate electrodes having sidewall spacers are formed on a substrate. After using the sidewall spacers to form self-aligned source / drain contacts and self-aligned silicide contacts, the sidewall spacers are removed. By removing the sidewall spacers, the aspect ratio of the gap between adjacent closely spaced gate electrodes is substantially reduced (from greater than 5 to less than 2), thereby preventing voids during the subsequent deposition of an ILD layer.

Description

BACKGROUND OF THE INVENTION[0002](1) Field of the Invention[0003]The present invention relates to a method for making integrated circuits on semiconductor substrates. The method is for forming interlevel dielectric (ILD) layers having improved gap filling between closely spaced conducting lines. In particular the method utilizes the removal of sidewall spacers on closely spaced FET gate electrodes after forming self-aligned lightly doped source / drain areas and source / drain contact areas, and before depositing an ILD layer.[0004](2) Description of the Prior Art[0005]As the Ultra-Large Scale Integration (ULSI) circuit density increases and device features sizes become less than 0.25 micrometers, increasing numbers of patterned electrically conducting levels are required with decreasing spacings between conducting lines at each level to effectively wire up discrete semiconductor devices on semiconductor chips. In the more conventional method the different levels of electrical interconn...

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Benefits of technology

[0008]A second objective of this invention is to reduce the aspect ratio of the gaps between these closely spaced conducting lines by removing the sidewall spacers or partially removing the sidewall spacers after forming the lightly doped source / drain areas and before depositing the ILD layers.

Problems solved by technology

In the conventional process for very-high density circuits with minimal feature sizes, the aspect ratio of the gaps between the gate electrodes having sidewall spacers can be very large (for example, greater than 5), and result in void formation during subsequent ILD layer deposition.

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