Bi-directional bus circuitry executing bi-directional data transmission while avoiding floating state

Abstract

A data bus included in a bi-directional bus circuitry is divided into a first bus node and a second bus node by a repeater circuit. The repeater circuit includes a first tristate buffer for amplifying and transmitting data from the first bus node to the second bus node, and a second tristate buffer connected in reverse direction. When the data bus is not used, the first and second tristate buffers are both activated, and the repeater circuit functions as a latch circuit. Therefore, in the bi-directional bus circuitry, even when the data bus is not used, the potential level of the data bus can be prevented from being left unfixed, ensuring stable operation.

Description

BACKGROUND OF THE INVENTION1. Field of the InventionThe present invention relate to a bi-directional bus circuitry and, more specifically, to a bi-directional bus circuitry used for a semiconductor device such as a microprocessor, capable of high speed and stable bi-directional data transmission.2. Description of the Background ArtAlong with the recent increase in scale of semiconductor devices such as an LSI and associated increase in chip size, bus lines for signal transmission within the semiconductor devices come to be longer. The longer bus line means increased parasitic resistance and parasitic capacitance, which present the problem of increased time of signal transmission over the bus lines.When the direction of signal transmission over a bus line is limited in one direction, the speed of transmission may be improved in a relatively simple manner, by inserting a repeater circuit functioning as a signal buffer appropriately into the elongated bus line. If the signal transmissi...

AI Technical Summary

Benefits of technology

The present invention provides a bi-directional bus circuitry that prevents the potential level of the data bus from being left unfixed when it is not being used. The circuitry includes a data bus, a potential fixing circuit, repeater circuits, and an arbiter circuit. The repeater circuits are arranged between adjacent bus nodes and each includes a first signal transmitting circuit and a second signal transmitting circuit. The arbiter circuit activates both circuits when data is not being transmitted between circuit blocks. This ensures that the potential level of each bus node is fixed, which prevents unstable operation and reduces parasitic capacitance. The invention provides a solution for stabilizing the operation of the bi-directional bus circuitry without the need for a special potential fixing circuit.

Problems solved by technology

The longer bus line means increased parasitic resistance and parasitic capacitance, which present the problem of increased time of signal transmission over the bus lines.

With the potential level of the bus node being unfixed, the potential level of the bus node comes to be the intermediate potential, possibly causing a constant current, which will be consumed wastefully, in the input and output buffers of the circuit blocks which are connected to the bus node.

If the potential of the bus node should be higher than a power supply potential, which corresponds to the H level potential of the data or lower than the ground potential which corresponds to the L level potential of the data because of a noise or the like, there is a possibility of circuit break down in the input and output buffers of the circuit blocks connected to the bus node.

As will be described in detail later, however, it is difficult to apply the technique for fixing the bus potential when not in use shown in FIG. 10, directly to a bi-directional bus circuitry.

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