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Phase interpolator with output amplitude correction

a phase interpolator and output amplitude technology, applied in the field of electronic devices, can solve problems such as errors in downstream circuitry

Inactive Publication Date: 2008-09-16
BROADCOM INT PTE LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

"The present invention is a device called a phase interpolator that generates a new clock signal by combining two input clock signals. The phase interpolator uses a weight value to determine the angle at which the new clock signal is generated. The device has two sides, each containing a current source and a switch, which are controlled by the weight value to adjust the amount of current passing through the device. The method involves applying the input clock signals to each side and receiving the new clock signal at the output. The technical effect of this invention is the ability to generate a precise and accurate clock signal with a simple and efficient device."

Problems solved by technology

This amplitude variation with interpolation angle can result in errors in downstream circuitry that relies on phase-interpolated output clock Z for its processing.

Method used

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  • Phase interpolator with output amplitude correction
  • Phase interpolator with output amplitude correction
  • Phase interpolator with output amplitude correction

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Embodiment Construction

[0018]As described above in reference to prior-art phase interpolator 100 of FIG. 1, the weighting value applied to switches 120-124 is the complement of the weighting value w applied to switches 114-118. For current sources 126-136, this means that the total current through phase interpolator 100 (i.e., the sum of the current through the A-side (the left side of FIG. 1) and the current through the B-side (the right side of FIG. 1)) is constant over the entire phase-interpolation range. As a result, the normalized magnitude of output signal Z is given by Equation (1) as follows:

Z=√{square root over (α2+(1−α)2)},  (1)

where α is the normalized interpolation angle (i.e., the interpolation angle in degrees divided by 90). The results plotted in FIG. 2 conform with Equation (1). On the other hand, to achieve constant amplitude of the interpolated output signal, the quadrature offset A and B components should be the sine and cosine functions, respectively, of the interpolation angle, such...

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Abstract

A phase interpolator generates a phase-interpolated output clock signal Z from two phase-offset input clock signals A and B, where the interpolation angle of the output clock is based on a weight value W. The phase interpolator has A-side and B-side circuitry, each having (1) an array of parallel current mirrors, (2) a block of parallel switches, where each switch is connected in series with a corresponding current mirror, and (3) an encoder that controls the corresponding switches based on the weight value W. The total current through the phase interpolator varies with interpolation angle, such that, for example, the variation in output amplitude with interpolation angle is reduced. In general, individual bit values in weight value W are not used to control individual switches for all interpolation angles.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to electronics, and, in particular, to phase interpolator circuits that generate a selected phase-interpolated output clock signal from two phase-offset input clock signals.[0003]2. Description of the Related Art[0004]FIG. 1 shows a schematic circuit diagram of a prior-art phase interpolator 100, which receives two phase-offset input clock signals A and B and generates a phase-interpolated output clock signal Z, whose phase is interpolated between the phases of clocks A and B based on a 3-bit weighting value w. In particular, input clock signals A and B and their complements are applied at the gates of NFETs 102-108, output clock signal Z and its complement appear at nodes 110 and 112, and the three bits of weight value w and their complements are applied to the gates of (NFET) switches 114-124. Each switch is connected in series to a corresponding (NFET) current source 126-136. The sizes o...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): H03H11/16
CPCH03K5/13H03K2005/00195H03K2005/00156H03K2005/00052
Inventor ABEL, CHRISTOPHER J.ANIDJAR, JOSEPHSINDALOVSKY, VLADIMIRZIEMER, CRAIG B.
Owner BROADCOM INT PTE LTD