Liquid crystal display device having balanced clock signal lines
a liquid crystal display and clock signal technology, applied in the direction of identification means, instruments, optics, etc., can solve the problem of ineffective reduction of electromagnetic radiation, and achieve the effect of reducing the electromagnetic radiation caused by clock signals
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first embodiment
. . . FIGS. 1 to 8
[0038]FIG. 1 is a diagram showing the schematic construction of a main part of a first embodiment according to the present invention. The first embodiment of the present invention is equipped with data driver ICs 15-1 to 15-10 (the data driver ICs 15-3 to 15-8 are omitted from the illustration) which are different in structure from the data driver ICs 2-1 to 2-10 shown in FIG. 19. Each of the data driver ICs 15-1 to 15-10 has a dummy terminal 16-1 to 16-10, and the other construction is designed to be well known.
[0039]Furthermore, the first embodiment is equipped with a timing controller 17 different in circuit construction from the timing controller 4 shown in FIG. 19. The timing controller 17 is designed to output a clock signal and another clock signal which is in reverse relation with the former clock signal. The latter clock signal thus reversed will be hereinafter referred to as a reverse clock signal. The other construction of the timing controller 17 is des...
second embodiment
. . . FIG. 10
[0069]FIG. 10 is a diagram showing the schematic construction of a main part of the second embodiment of the present invention. The second embodiment of the present invention is equipped with a timing controller 17 shown in FIG. 1. Furthermore, a reverse clock signal line 79 for transmitting a reverse clock signal output from the timing controller 17 is equipped in parallel to the clock signal line 9, and also a terminating circuit 80 is equipped to the terminal portion of the reverse clock signal line 79.
[0070]In FIG. 10, (i) represents a circuit construction of the terminating circuit 80, reference numerals 81, 82 represent terminating resistors, and reference numerals 83, 84 represent capacitors equipped so that the load capacitance of the reverse clock signal line 79 is equal or substantially equal to the load capacitance of the clock signal line. The composite capacitance value of the capacitors 83, 84 are set as the total values of the clock input capacitance of t...
third embodiment
. . . FIGS. 11 to 14
[0072]FIG. 11 is a diagram showing the schematic construction of a main part of a third embodiment according to the present invention. In FIG. 11, reference numeral 85 represents a data signal line for odd-number dots through which data signals of odd-number dots are transmitted, and reference numeral 86 represents a data signal line for even-number dots through which data signals of even-number dots are transmitted.
[0073]The third embodiment of the present invention is equipped with a timing controller 87 and data driver ICs 88-1 to 88-10 which are different in construction from the timing controller 17 and the data driver ICs 15-1 to 15-10 shown in FIG. 1. The data driver ICs 88-3 to 88-8 are omitted from the illustration.
[0074]The timing controller 87 is designed so that the data signals of the even-number dots are output while the phase thereof is shifted by 180 degrees with respect to the data signals of the odd-number dots, and the other construction is the...
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