Method for gate height control in a gate last process

Abstract

Provided is a method that includes forming first and second gate structures in first and second regions, respectively, the first gate structure including a first hard mask layer having a first thickness and the second gate structure including a second hard mask layer having a second thickness less than the first thickness, removing the second hard mask layer from the second gate structure, forming an inter-layer dielectric (ILD) over the first and second gate structures, performing a first chemical mechanical polishing (CMP), remove the silicon layer from the second gate structure thereby forming a first trench, forming a first metal layer to fill the first trench, performing a second CMP, remove the remaining portion of the first hard mask layer and the silicon layer from the first gate structure thereby forming a second trench, forming a second metal layer to fill the second trench, and performing a third CMP.

Description

PRIORITY DATA[0001]This application claims priority to Provisional Application Ser. No. 61 / 103,021 filed on Oct. 6, 2008, entitled “Method for Gate Height Control in a Gate Last Process,” the entire disclosure of which is incorporated herein by reference.BACKGROUND[0002]As technology nodes shrink, in some IC designs, there has been a desire to replace the typically polysilicon gate electrode with a metal gate electrode to improve device performance with the decreased feature sizes. Providing metal gate structures (e.g., including a metal gate electrode rather than polysilicon) offers one solution. One process of forming a metal gate stack is termed “gate last” process in which the final gate stack is fabricated “last” which allows for reduced number of subsequent processes, including high temperature processing, that must be performed after formation of the gate. Additionally, as the dimensions of transistors decrease, the thickness of the gate oxide must be reduced to maintain perf...

AI Technical Summary

Problems solved by technology

There are challenges to implementing such features and processes in CMOS fabrication however.

For example, in a “gate last” fabrication process, problems have arisen with control of the gate height due to factors such as a loading effect of nMOS and pMOS devices and non-uniformity of a chemical mechanical polishing (CMP) process.

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