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Memory apparatus with multi-level cells and operation method thereof

a memory apparatus and multi-level technology, applied in the field of memory apparatus and an operation method thereof, can solve the problems of relatively high probability of occurrence of write operation errors or read operation errors thereof, and achieve the effect of excessive density of threshold voltage distributions

Active Publication Date: 2013-02-26
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention is about a way to reduce errors in a memory caused by too many threshold voltage distributions. It does this by encoding the input data to increase the space between threshold voltage distributions, which makes it easier to sense the data. This results in a larger sensing window and reduces the chance of errors during both writing and reading of the memory.

Problems solved by technology

Therefore, regarding a flash memory whose a single MLC stores more bits, an occurrence chance of write operation errors or read operation errors thereof is relatively high.
Therefore, how to reduce the occurrence chance of the write operation errors or the read operation errors caused by lessening of the sensing window in a MLC flash memory is a major problem to be resolved.

Method used

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  • Memory apparatus with multi-level cells and operation method thereof
  • Memory apparatus with multi-level cells and operation method thereof
  • Memory apparatus with multi-level cells and operation method thereof

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Embodiment Construction

[0037]Referring to FIGS. 3A and 3B, FIG. 3A is a block diagram illustrating a memory apparatus 100 according to an embodiment of the present invention, and FIG. 3B is a block diagram of a memory 120 of the memory apparatus 100. The memory apparatus 100 includes a controller 110, the memory 120, a read / program circuit 136, and a sensing reference system 180. In the present embodiment, the memory 120 has a first block 121, a second block 122, a third block 123, and a fourth block 124. The first block 121 has a plurality of multi-level cells (MLCs) 126. Each of the MLCs 126 is used for storing two or more bits of data. For example, in the following embodiment, each of the MLCs 126 stores four bits of data, though the present invention is not limited thereto. Each of the MLCs 126 stores an encoded subset 502. Moreover, the second block 122 stores a target encoding code 504, the third block 123 stores a sensing reference code 506, and the fourth block 124 stores an error correction code ...

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Abstract

A memory apparatus and an operation method thereof are provided. The memory apparatus includes a plurality of multi-level cells and a controller. The controller encodes input data according to a target encoding code to generate a plurality of encoded subsets, and stores the encoded subsets into the multi-level cells. Thereafter, the controller could read data from the multi-level cells, perform an error correction procedure on the read data to correct and recover the read data as recovered data, and decode the recovered data according to the target encoding code. Consequently, sensing windows between threshold voltage distributions of the multi-level cells are expanded.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to a memory apparatus and an operation method thereof. More particularly, the present invention relates to a memory apparatus of a flash memory with multi-level cells (MLCs), and an operation method thereof.[0003]2. Description of Related Art[0004]A flash memory is one kind of non-volatile memories, which can maintain stored data without power. The flash memories are categorized into NOR flash memories and NAND flash memories. Moreover, the flash memories can also be categorized into single level cell (SLC) flash memories and multi level cell (MLC) flash memories according to an amount of bits capable of being stored in a single memory cell. Wherein, the “single level” represents that each of the memory cells only records data of one bit, and the “multi level” represents that each of the memory cells records data of multiple bits. Since the MLC records more data bits compared to the SLC, th...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): G11C29/00G11C11/34
CPCG06F11/1072G11C16/34G11C11/5621
Inventor CHEN, CHUNG-KUANG
Owner MACRONIX INT CO LTD