High-frequency IC multi-bus knot tying structure and method

Abstract

The presetn invention relates to a multiple column wire wiring structure of high-frequency integrated circuit and its method. Said structure has first electronic component, second electronic component, chip and and several metal wires, in which the first electronic component is fit on the second electronic component by means of chip pad, said structure also includes wiring pads and coplanar wiring pad, and the metal wires are divided into signal wires and ground wires, these metal wires at least can be divided into first column of wires and second column of wires. Said invention also provides the method for implementing said invented multiple column wire wiring structure.

Description

technical field [0001] The invention relates to a high-frequency integrated circuit bonding structure and method, in particular to a high-frequency integrated circuit multi-row wire bonding structure and method that enable the electrical connection between electronic components to have the best electrical characteristics. Background technique [0002] At present, since wire bonding is a relatively cheap and robust circuit connection method, wire bonding is the most commonly used method for circuit connection between IC chips and circuit parts in electronic products. As the operating frequency of electronic products increases day by day, the parasitic inductance and capacitance generated by wire bonding often directly impact the electrical characteristics between the IC chip and the circuit, which cannot be ignored. Therefore, it is worth paying attention to how to reduce these parasitic effects to avoid the decline of electrical characteristics between IC chips and circuits ...

AI Technical Summary

Problems solved by technology

[0006] As can be seen from the above, the wire bonding structure in FIG. 1 exposes the following disadvantages: since the pins 160-180 have a considerable distance (usually greater than 0.5mm) between the pins, the chip 110 end to the pin 160 Between -180 terminals, the pitch between metal lines 130-150 increases significantly

[0008] However, although in FIG. 2 the grounding point is set on the exposed part of the chip pad 220 outside the chip 240, the grounding path can be reduced, but the design of the sequential arrangement of the metal lines 270-277 will still generate relatively large electromagnetic interference, which will affect the overall circuit characteristics

Images