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Solid camera

A technology of solid-state and reset transistors, which is applied in the direction of electric solid-state devices, radiation control devices, semiconductor devices, etc., and can solve the problem of reducing the total number of wiring

Inactive Publication Date: 2007-11-07
コラボイノベーションズインコーポレイテッド
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in order to increase the aperture ratio of each pixel in the case of advances in the miniaturization of pixels, it is necessary to reduce the total number of wires

Method used

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Experimental program
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Embodiment Construction

[0031] Next, a solid-state imaging device according to an embodiment of the present invention will be described.

[0032] FIG. 1 shows an example of the configuration of an enlarged unit pixel of the solid-state imaging device of the present invention. In FIG. 1, 1 is a photodiode (PD), 2 is a readout transistor, FD is a floating diffusion, 3 is a reset transistor, 4 is a detection transistor, 6 is a signal line, 7 is a drain line (VDD), and 15 is a drain line (VDD). 16 is a gate line serving as both readout and reset, and 17 is an FD line connecting the FD portion and the gate of the detection transistor 4 . Assuming that the gate line 16 serving both readout and reset is an integer N, the gate of the readout transistor 2 of the pixel in the Nth row is connected to the gate of the reset transistor 3 of the pixel in the (N+1)th row. The detection transistor 4 is connected to a signal line 6 different for each column. Furthermore, a VDD power supply pulse different for each r...

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Abstract

In a MOS type sensor including a floating diffusion (FD) amplifier in each pixel, the number of pulse lines is reduced, so as to improve the numerical aperture. For this purpose, a read pulse for a read transistor of a first pixel and a reset pulse for a reset transistor of a second pixel adjacent to the first pixel in a column direction are supplied through a common gate line; a LOW level potential of a drain line connected to a drain region (a region for supplying a pulse voltage to an FD portion through the reset transistor) of the first pixel is set to a potential higher than a potential depth of a photodiode of the first pixel in resetting the second pixel; and potential below the gate of the reset transistor of the first pixel obtained by applying a LOW level voltage to this gate is set to a potential higher than the LOW level potential of the drain line.

Description

technical field [0001] The present invention relates to a MOS type solid-state imaging device used in digital cameras and the like. Background technique [0002] FIG. 17 shows an example of a conventional solid-state imaging device composed of MOS transistors. In this solid-state imaging device, a plurality of photodiodes (PD) 1, readout transistors 2, floating diffusion (FD) portions, reset transistors 3, detection transistors 4, and address transistors 5 are provided on a semiconductor substrate. The solid-state imaging device in which the enlarged unit pixels are arranged as a photosensitive area 14 of a two-dimensional shape, and is composed of a signal line 6, a drain line 7, a readout gate line 8, a reset gate line 9, an address gate line 10, and a selection gate line. The vertical shift register 12 for the pixel row, the horizontal shift register 13 for selecting the pixel column, and the timing generation circuit 11 for supplying necessary pulses to the two shift re...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/146H04N5/225H04N25/00
CPCH01L27/14603H04N3/1512H01L27/14643H04N5/335H04N25/00H04N25/766H04N25/76
Inventor 山口琢己菰渕宽仁
Owner コラボイノベーションズインコーポレイテッド