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Lateral junction field-effect transistor and its manufacturing method

A field effect transistor, bonding technology, used in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of reduced ON resistance, limited expansion range of spacing, and limited expansion range, and achieves reduced ON resistance. Effect

Inactive Publication Date: 2008-04-02
SUMITOMO ELECTRIC IND LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] However, in the structure shown in Figure 72, in order to reduce the ON resistance, the p + After the distance between the uppermost part of the epitaxial layer 112 and the lowermost part of the gate contact layer 130 is expanded, the absolute value of the gate voltage required for OFF will become larger, so the expansion range of the distance is limited, and the reduction of ON resistance is also limited.
[0009] In addition, as a normally-off type, the interval must be smaller than the interval of the depletion layer expanded under the action of the diffusion potential in the junction of the channel layer 114 and the gate contact layer 130, so naturally, the expansion range of the interval limited, the reduction in ON resistance is also limited

Method used

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  • Lateral junction field-effect transistor and its manufacturing method
  • Lateral junction field-effect transistor and its manufacturing method
  • Lateral junction field-effect transistor and its manufacturing method

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no. 1 Embodiment approach

[0180] (Structure of Horizontal Junction Field Effect Transistor 100)

[0181] Next, referring to FIG. 1 , the structure of a lateral junction field effect transistor 100 according to a first embodiment of the present invention will be described.

[0182] The structural feature of the horizontal junction field effect transistor 100 in the first embodiment of the present invention is that the pn junction and the gate electrode layer are vertically arranged. In this specification, the longitudinal direction means the direction along the depth of the substrate, and the lateral side means the direction parallel to the main surface of the substrate.

[0183] The horizontal junction field effect transistor 100 is provided with a first semiconductor layer 11 containing p-type impurities on a semiconductor substrate 2 made of Si or the like; on the first semiconductor layer 11, the concentration of n-type impurities is higher than The second semiconductor layer 12 of the impurity con...

no. 2 Embodiment approach

[0202] (Structure of Horizontal Junction Field Effect Transistor 200)

[0203] Next, referring to FIG. 8, the structure of the lateral junction field effect transistor 200 in the second embodiment will be described.

[0204] The structural feature of the horizontal junction field effect transistor 200 in the present embodiment is that the pn junction and the gate electrode layer are vertically arranged like the horizontal junction field effect transistor 100 .

[0205] The horizontal junction field effect transistor 200 is provided with a first semiconductor layer 21 containing p-type impurities on a semiconductor substrate 2 made of Si or the like; on the first semiconductor layer 21, the concentration of n-type impurities containing The second semiconductor layer 22 of the impurity concentration of the first semiconductor layer 21; the third semiconductor layer 23 on the second semiconductor layer 22 containing p-type impurities; the third semiconductor layer 23 on the third...

no. 3 Embodiment approach

[0229] (Structure of Horizontal Junction Field Effect Transistor 300)

[0230] Next, referring to FIG. 17 , the structure of the lateral junction field effect transistor 300 in the third embodiment will be described.

[0231] The structural feature of the horizontal junction field effect transistor 300 in this embodiment is that the pn junction and the gate electrode layer are vertically arranged as in the horizontal junction field effect transistor 100 .

[0232]The horizontal junction field effect transistor 300 is provided with a first semiconductor layer 31 containing p-type impurities on a semiconductor substrate 2 made of Si or the like; on the first semiconductor layer 31, the concentration of n-type impurities containing The second semiconductor layer 32 of the impurity concentration of the first semiconductor layer 31; the third semiconductor layer 33 on the second semiconductor layer 32 containing p-type impurities; the third semiconductor layer 33 on the third semic...

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Abstract

A lateral junction field effect transistor includes a first gate electrode layer (18A) arranged in a third semiconductor layer (13) between source / drain region layers (6, 8), having a lower surface extending on the second semiconductor layer (12), and doped with p-type impurities more heavily than the second semiconductor layer (12), and a second gate electrode layer (18B) arranged in a fifth semiconductor layer (15) between the source / drain region layers (6, 8), having a lower surface extending on a fourth semiconductor layer (14), having substantially the same concentration of p-type impurities as the first gate electrode layer (18A), and having the same potential as the first gate electrode layer (18A). Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.

Description

technical field [0001] The invention relates to a lateral junction field effect transistor, in particular to the structure and manufacturing method of the lateral junction field effect transistor capable of reducing ON resistance while maintaining good withstand voltage performance. Background technique [0002] The horizontal junction field effect transistor (hereinafter referred to as "JFET (Junction Field Effect Ttansistor)") is applied with a reverse bias voltage from the gate electrode to the pn junction provided on the side of the channel region through which carriers pass. The depletion layer from the pn junction diffuses to the channel region, controls the conductance of the channel region, and performs switching and other actions. Among them, the horizontal JFET refers to making the carriers in the channel region move parallel to the surface of the element. [0003] The carriers in the channel can be either electrons (n-type) or holes (p-type). However, in the JFE...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/808H01L21/337
CPCH01L29/1058H01L29/808H01L29/66893H01L29/0634H01L29/42316H01L29/1066
Inventor 藤川一洋原田真弘津研一初川聪星野孝志松波弘之木本恒畅
Owner SUMITOMO ELECTRIC IND LTD