Bitline precharging circuit and method

Abstract

An architecture and method for fast precharge of bitlines in a densely packed, dynamic content addressable memory is disclosed. The dynamic content addressable memory cells are arranged according to an open bitline architecture to obtain high packing density. The bitlines are precharged through equalization between every two adjacent open bitline pairs. More specifically, a bitline and its adjacent neighbouring bitline on the same side of the bitline sense amplifiers are equalized at several locations along the bitlines such that they are equalized at high speed, which is typically not available in open bitline architectures. Hence the adjacent bitlines are precharged in a manner similar to a folded bitline architecture. Additional equalization circuits are connected between the complementary bitlines of each open bitline pair, therefore during the precharge phase, all four bitlines of the two open bitline pairs are equalized with each other. To ensure that all four bitlines equalize to the midpoint voltage level, complementary logic levels are written to the bitlines prior to equalization.

Description

technical field [0001] The present invention relates to content addressable memory (CAM). More particularly, the present invention relates to a circuit and method for high-speed precharging of bit lines in an open bit line structure CAM device. Background technique [0002] In many conventional memory systems, such as random access memory, binary digits (bits) are stored in memory cells and are accessed by a processor specifying the linear address associated with a given cell. Such a system provides fast access to any part of the memory system within certain constraints. To facilitate control by the processor, each operation to access memory must specify, as part of the instruction, the address of the desired memory location. Standard storage systems are not well designed for search-based content. Content-based searches in standard memory require software-based algorithmic searches under microprocessor control. To perform a search, many memory operations are required. T...

AI Technical Summary

Problems solved by technology

However, the trivariate CAM memory array using the open bit line structure is not suitable for high-speed applications due to its slow pre-charging speed

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