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Gate oxide process methods for high performance mos transistors by reducing remote scattering

A MOS transistor and gate technology, which is applied in the field of field effect transistor manufacturing, can solve the problems of affecting the transistor speed, reducing carrier mobility, disadvantages, etc.

Inactive Publication Date: 2008-04-09
GLOBALFOUNDRIES U S INC MALTA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] While a high-k dielectric material acting as a gate insulator does reduce leakage current, this material tends to detrimentally reduce carrier mobility, negatively impacting transistor speed

Method used

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  • Gate oxide process methods for high performance mos transistors by reducing remote scattering
  • Gate oxide process methods for high performance mos transistors by reducing remote scattering
  • Gate oxide process methods for high performance mos transistors by reducing remote scattering

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Embodiment Construction

[0029] Referring to the figures, the present invention will be explained below. Like components in the diagrams are labeled with like reference numerals. The present invention provides a MOS transistor structure, and a method of fabrication, that employs a gate insulator capable of reducing gate leakage while at the same time alleviating the negative impact of prior art structures on the transistor's carrier mobility, thereby increasing transistor speed .

[0030] refer to image 3 , image 3 A fragmentary cross-sectional view is shown showing an LDD type MOS transistor 200 according to one aspect of the present invention, wherein source and drain regions 108, 112, extension regions 104, 106, and isolation region 121 are located in a silicon substrate 102. The source and drain regions 108, 112 (and their associated extension regions in this example) are laterally separated or spaced from each other, thereby defining a channel region 201 therebetween in the silicon substrate. ...

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Abstract

The present invention relates to a MOS transistor structure and method of manufacture which provides a high-k dielectric gate insulator for reduced gate current leakage while concurrently reducing remote scattering, thereby improving transistor carrier mobility.

Description

technical field [0001] The present invention relates to the fabrication of field effect transistors of reduced body size; in particular to processes for fabricating transistors with gate insulators that reduce leakage current while improving carrier mobility by reducing scattering. Background technique [0002] In the ever-advancing integrated circuit (IC) technology, reducing the physical size of the IC has long been regarded as an important goal. Reducing the body size of the IC reduces areal capacitance and facilitates higher speed performance of the IC. Furthermore, reducing the IC die area results in providing more die per semiconductor wafer, leading to increased yields in IC manufacturing. This advantage is the driving force for ever-decreasing IC body size. [0003] Referring to FIG. 1 , a typical component of a single-chip IC is a metal-oxide-semiconductor (MOS, hereinafter referred to as MOS) transistor 100 fabricated in or on a semiconductor substrate 102 . The...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/00H01L29/51H01L29/49H01L21/283H01L21/28H01L29/423H01L29/78
CPCH01L29/4916H01L29/495H01L29/513H01L21/28194Y10S977/881H01L29/517H01L29/7833H01L29/516
Inventor 金铉席J·杰昂
Owner GLOBALFOUNDRIES U S INC MALTA