Method for realizing site programmeable gate array loading

Abstract

The present invention realizes loading to FPGA through loading control register in slow speed interface chip, which includes A, reading loading control register value and storing in high-speed memory; B, to proceed logical operation to value in said high-speed memory and writing calculation result into loading control register, to realize locking loaded data to FPGA; C, judging whether existing need loading data, if existing then to step B, otherwise ending loading process to FPGA. The present invented method can reduce visiting times to slow speed interface chip and raise loading speed to FPGA.

Description

technical field [0001] The invention relates to the field of programmable logic devices, in particular to a method for realizing loading of a field programmable gate array (Field Programmable Gate Array, FPGA). Background technique [0002] The emergence of FPGA devices is the result of the development of VLSI technology and computer-aided design technology. FPGA devices are highly integrated and small in size, and can realize special application functions through user programming. It allows circuit designers to use a computer-based development platform to go through design entry, simulation, testing, and verification until the desired function is achieved. [0003] After the FPGA device is powered on, it will be able to work normally. It needs to be used as the central processing unit (CPU) of the single board of the FPGA development platform to load the prepared program on the FPGA in a serial manner. The loading process needs to pass through the peripheral of the CPU. i...

AI Technical Summary

Problems solved by technology

The bus frequency of EPLD's local bus is generally 25MHz, and the maximum does not exceed 50MHz, which is far lower than the CPU main frequency and FPGA loading clock frequency. Frequent access to EPLD during the loading process of FPGA will inevitably greatly reduce the loading rate.

Therefore, the disadvantages of the existing method of loading FPGA through low-speed peripheral interface chips such as EPLD are low efficiency and long loading time, and are not suitable for occasions requiring fast loading.

[0016] In order to improve the loading rate of FPGA, high-speed peripheral interface chip can be used to realize FPGA loading, but there is no ready-made high-speed peripheral interface chip for FPGA loading, and the use of high-speed peripheral interface chip will greatly increase the cost

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