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Method for manufacturing semiconductor device

A manufacturing method and semiconductor technology, applied in the fields of semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of increasing costs and complex manufacturing process steps, and achieve the effect of reducing production costs and reducing manufacturing process steps.

Inactive Publication Date: 2008-06-11
POWERCHIP SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0013] In the above process, the MIM capacitor is formed first, and then the metal interconnection (dual damascene structure) is formed. Since multiple metal layer deposition processes, chemical mechanical polishing processes, and photolithography etching processes are required, the steps of the manufacturing process are more complex. complex and costly

Method used

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  • Method for manufacturing semiconductor device
  • Method for manufacturing semiconductor device
  • Method for manufacturing semiconductor device

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Embodiment Construction

[0037] Next, the embodiments of the present invention will be described in detail, and the embodiments will be explained with the accompanying drawings. Wherever possible, the same or like reference numbers are used in the drawings to describe the same or like parts. It should be noted that the depictions are in simplified form and not exact dimensions.

[0038] Figures 3A to 3F The figure shows a cross-sectional view of the manufacturing process of a semiconductor device according to a preferred embodiment of the present invention.

[0039] Please refer to Figure 3A , The present invention provides a method for manufacturing a semiconductor element. First, a substrate 300 is provided, and a metal layer 302 and a metal layer 304 have been formed in the substrate 300 . The material of the metal layer 302 and the metal layer 304 is, for example, copper metal or aluminum metal.

[0040] Next, a sealing layer 306 is formed on the substrate 300 to cover the metal layer 302 a...

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Abstract

The manufacture method for a semiconductor element comprises: providing a substrate with formed first and second metal layers, forming by turns the first and second dielectric layers, an etching-end layer with a first and second openings on upper of first and second metal layers, respectively; removing dielectric layers to form the first groove to expose the first metal layer; forming capacity dielectric layer on substrate with the third opening on upper of second metal layer; removing the capacity dielectric layer and said two dielectric layers to form opening to expose the second metal layer; then, filling metal in first groove and opening.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor element, in particular to a method for manufacturing a semiconductor element suitable for simultaneously forming a double damascene structure and a MIM capacitor. Background technique [0002] With the increase of the integration level of semiconductor components, and entering the deep sub-micron (Deep Sub-Micron) process, the size of the components is gradually reduced, and the space for capacitors is relatively smaller and smaller. The capacitance of the capacitor depends on the size of the surface area between the upper electrode and the lower electrode. Therefore, there are currently two main methods used to solve the problem of shrinking semiconductor capacitors and increasing the capacity, namely, selecting a dielectric layer with high capacitance and increasing the surface area of ​​the lower electrode of the capacitor. [0003] When using a high dielectric constant material in...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/02H01L21/82H01L21/768
Inventor 张格滎黄丘宗
Owner POWERCHIP SEMICON CORP