Method and apparatus for calibrating acceptable deviation of maximum jitter

Abstract

The invention provides a phase-locked loop maximum vibration allowable error calibrating method and its device. The phase-locked loop includes a phase detector and a charge dipper set in series. The method provides a first correcting signal and a second one for the phase detector to detect the phases, then according to the phase difference between the two correct signals to generate a rising pulse and a descending pulse to control the charge dipper so as to generate a net current, and uses a correcting unit to selectively adjust the width of the rising or descending pulse according to the net current until the net current reaches an object value, so as to calibrate the vibration error caused by the property curves of the phase detector and charge dipper.

Description

technical field [0001] The invention relates to a method and device for calibrating the maximum jitter tolerance deviation of a phase-locked loop, in particular to a calibration method that can effectively calibrate the characteristic deviation of the internal circuit of the phase-locked loop so that the phase-locked loop has the maximum jitter tolerance deviation and its devices. Background technique [0002] Such as figure 1 Shown is a typical PLL system 1, which includes a phase detector 11, a charge extractor 12, a loop filter 13, a voltage-controlled oscillator (VCO) 14 and a Divider 15. The mode of operation of this phase-locked loop system 1 is that the phase detector 11 detects the phase difference between an input signal IN and a clock signal CLK generated by a voltage-controlled oscillator 14 and properly divided by a frequency divider 15, and according to the phase difference between the two The phase difference between them generates a rising pulse UP and a fa...

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Problems solved by technology

[0003] However, in the general PLL system 1, the transfer curves of the phase detector 11 and the charge extractor 12 are usually not ideal, so that the phase lock point is shifted on the transfer curve, resulting in a reduction in the jitter tolerance, and such as figure 2 In the situation shown, the phase lock point is the point A shown in the figure, that is, the point where the phase difference is zero, and the positive phase jitter tolerance error of point A is greater than 1T, but the maximum negative phase jitter tolerance error is only -0.625 T, however, in an ideal situation, the phase lock point should be at point B in the diagram, and its positive and negative phase jitter tolerance errors will be 1T and -1T respectively

Therefore, if the transfer curves of the phase detector 11 and the charge extractor 12 are not ideal, the maximum jitter allowable deviation will be reduced, resulting in poor phase-locking capability of the phase-locked loop.

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